LAN8810 Datasheet, PDF (56/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
4.3.5 RECEIVE ERROR-FREE PACKETS COUNTER MID REGISTER
Index:
U3
Size:
16 bits
Bits
Description
15:0 RCVGPKT[31:16]
Counts the received error-free packets.
Contains the 16 middle bits of the 48-bit counter.
Type
RO
Default
0000h
Note:
The 48-bit receive error-free packets counter is split across 3 registers. In order to read the counter cor-
rectly, the registers must be read in the following order: Receive Error-Free Packets Counter Low Register,
Receive Error-Free Packets Counter Mid Register, Receive Error-Free Packets Counter High Register.
After reading the high register, the counter will be automatically cleared.
4.3.6 RECEIVE ERROR-FREE PACKETS COUNTER LOW REGISTER
Index:
U4
Size:
16 bits
Bits
Description
15:0 RCVGPKT[15:0]
Counts the received error-free packets.
Contains the 16 low-order bits of the 48-bit counter.
Type
RO
Default
0000h
Note:
The 48-bit receive error-free packets counter is split across 3 registers. In order to read the counter cor-
rectly, the registers must be read in the following order: Receive Error-Free Packets Counter Low Register,
Receive Error-Free Packets Counter Mid Register, Receive Error-Free Packets Counter High Register.
After reading the high register, the counter will be automatically cleared.
DS00001870B-page 55
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