LAN8810 Datasheet, PDF (46/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
Bits
Description
2
Power Optimization Disable
0 = Automatic power optimization is enabled
1 = Automatic power optimization is disabled (power consumption is
maximum)
1
RESERVED
0
LRST
Logic reset. This bit generates a reset that put all the logic into a known
state, but DOES NOT affect the register sets and 10/100 circuits. This bit is
NOT a self-clearing bit. Writing "1" to this bit generates synchronous reset.
Type
R/W
RO
RO
Default
0b
-
-
4.2.14 10/100 MODE CONTROL/STATUS REGISTER
Index (In Decimal): 17
Size:
16 bits
Bits
Description
15 EDSHORT
Energy Detect Short detection mode
0 = Normal detect mode
1 = Short detect mode
14 FASTRIP
10BASE-T fast mode
0 = normal operation
1 = activates PHYT_10 test mode
13 EDPWRDOWN
Enable the Energy Detect Power-Down mode
0 = Energy Detect Power-Down is disabled
1 = Energy Detect Power-Down is enabled
12 ED Power Down Mode
Select energy detect power down mode
0 = ED power down mode without NLP transmission
1 = ED power down mode with NLP transmission
11:8 RESERVED
7
Speed Optimize Enable
0 = Disable Speed Optimize
1 = Enable Speed Optimize
Note: Refer to Section 3.9.5, "Speed Optimizer," on page 29 for additional
information.
6
AutoNeg NP Enable
0 = Next page is disabled in the auto-negotiation process
1 = Next page is enabled in the auto-negotiation process
5
Auto MDIX Disable
0 = Auto Xover is enabled
1 = Auto Xover is disabled selection is done manually
Type
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
Default
0b
0b
0b
0b
-
0b
1b
0b
DS00001870B-page 45
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