LAN8810 Datasheet, PDF (19/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
3.4 Serial Management Interface (SMI)
The Serial Management Interface is used to control the device and obtain its status. This interface supports the standard
PHY registers required by Clause 22 of the 802.3 standard, as well as “vendor-specific” registers allowed by the spec-
ification. Non-supported registers (such as 11 to 14) will be read as hexadecimal “FFFF”. Device registers are detailed
in Section 4.0, "Register Descriptions," on page 34.
At the system level, SMI provides 2 signals: MDIO and MDC. The MDC signal is an aperiodic clock provided by the
station management controller (SMC). MDIO is a bi-directional data SMI input/output signal that receives serial data
(commands) from the controller SMC and sends serial data (status) to the SMC. The minimum time between edges of
the MDC is 160 ns. There is no maximum time between edges. The minimum cycle time (time between two consecutive
rising or two consecutive falling edges) is 400 ns. These modest timing requirements allow this interface to be easily
driven by the I/O port of a microcontroller.
The data on the MDIO line is latched on the rising edge of the MDC. The frame structure and timing of the data is shown
in Figure 1-1 and Figure 1-2. The timing relationships of the MDIO signals are further described in Section 5.5.6, "SMI
Timing," on page 73.
FIGURE 3-2:
MDIO TIMING AND FRAME STRUCTURE - READ CYCLE
Read Cycle
MDC
MDIO
32 1's 0 1
Preamble
Start of
Frame
10
OP
Code
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
D15 D14
PHY Address
Register Address
Turn
Around
...
...
Data
D1 D0
Data To Phy
Data From Phy
FIGURE 3-3:
MDIO TIMING AND FRAME STRUCTURE - WRITE CYCLE
Write Cycle
MDC
MDIO 32 1's 0 1
Preamble
Start of
Frame
01
OP
Code
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
D15 D14
PHY Address
Register Address
Turn
Around
...
...
Data
D1 D0
Data To Phy
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DS00001870B-page 19