LAN8810 Datasheet, PDF (47/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
Bits
Description
4
Auto Next Page Disable
Setting this bit disables automatic next page exchange in 1000BASE-T.
Advertising of next pages then depends on the value of the Next Page bit of
the Auto Negotiation Advertisement Register. In this case, if Next Page is
cleared, only the base page is sent.
0 = Normal operation
1 = Automatic next page is disabled
3:2 RESERVED
1
ENERGYON
This bit indicates whether energy is detected on the line. It is reset to “1” by
a hardware reset. When a software reset is asserted, this bit is cleared. If
this bit was set prior to a software reset, it will cause the INT7 bit of the
Interrupt Source Flags Register to be set. Therefore, after a software or
hardware reset, the INT7 bit should be cleared by writing a “1” to it.
Refer to Section 3.5, "Interrupt Management," on page 21 for additional
ENERGYON information.
0
Semi Crossover Enable
Setting this register enables semi cross over.
0 = Disable Semi cross over
1 = Enable Semi cross over
Note: Refer to Section 3.2, "HP Auto-MDIX," on page 16 for additional
information.
4.2.15 10/100 SPECIAL MODES REGISTER
Type
R/W
RO
RO
R/W
Index (In Decimal): 18
Size:
16 bits
Default
0b
-
1b
0b
Bits
Description
15 Enable RXDV Early Assertion
Setting this bit enables early assertion of RXDV in 10BASE-T. RXDV is
asserted before the SFD.
0 = Disable
1 = Enable
14 10BT HD Loopback Disable
Setting this bit disables MII loopback in 10BASE-T half duplex mode.
0 = normal operation
1 = activates PHYT_10 test mode
13:8 RESERVED
7
CRC Error Counter Data Source
Setting this bit changes the data source of the 1000BASE-T CRC error
counter.
0 = Data source in 1000BASE-T received data
1 = Data source in 1000BASE-T transmitted data
6
MCLK25EN
Enable an 25Mhz MAC clock output.
0 = 125MHz
1 = 25MHz
5
RESERVED
Type
R/W
Default
0b
R/W
NASR
000000b
RO
-
R/W
0b
RO
0b
RO
-
 2009-2015 Microchip Technology Inc.
DS00001870B-page 46