LAN8810 Datasheet, PDF (23/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
3.8.1.1 Configuration Straps
Configuration straps are multi-function pins that are driven as outputs during normal operation. During a Hardware
Reset (nRESET), these outputs are tri-stated. The high or low state of the signal is latched following de-assertion of the
reset and is used to determine the default configuration of a particular feature. Table 3-4 details the configuration straps.
Configuration straps are also listed as part of Section 2.0, "Pin Description and Configuration," on page 5 with underlined
names.
Configuration straps include internal resistors in order to prevent the signal from floating when unconnected. If a partic-
ular configuration strap is connected to a load, an external pull-up or pull-down should be used to augment the internal
resistor to ensure that it reaches the required voltage level prior to latching. The internal resistor can also be overridden
by the addition of an external resistor.
Note 1: The system designer must guarantee that configuration straps meet the timing requirements specified in
Section 5.5.3, "Power-On Hardware Reset Timing," on page 67. If configuration straps are not at the correct
voltage level prior to being latched, the device may capture incorrect strap values.
2: Configuration straps must never be driven as inputs. If required, configuration straps can be augmented, or
overridden with external resistors.
TABLE 3-5: CONFIGURATION STRAPS
Configuration
Strap
HPD_MODE
Description
Selects the hardware power-down (HPD) mode
Logic 0
(PD)
HPD with PLL
disabled (Default)
Logic 1
(PU)
HPD with PLL
enabled
3.8.1.2 CONFIG[3:0] Configuration Pins
The device provides 4 dedicated configuration pins, CONFIG[3:0], which are used to select the default SMI address and
mode of operation. The CONFIG[3:0] configuration pins differ from configuration straps in that they are single-purpose
pins and have different latch timing requirements. The high or low states of the CONFIG[3:0] pins are latched following
deassertion of a Hardware Reset (nRESET). Refer to Section 5.5.3, "Power-On Hardware Reset Timing," on page 67
for additional CONFIG[3:0] timing information.
Each CONFIG[3:0] configuration pin can be connected in one of four ways. The Configuration Pin Value (CPV) repre-
sented by each connection option is shown in Table 3-5.
TABLE 3-6: HARDWARE CONNECTION DETERMINES
CONFIGURATION PIN VALUE (CPV)
CONFIG[X]
Connects to:
GND
100_LED
1000_LED
VDD
Value
CPV(0)
CPV(1)
CPV(2)
CPV(3)
Using the CPV nomenclature for each CONFIG[3:0] pin, Section 3.8.1.2.1 describes how to configure the SMI address
and Section 3.8.1.2.2 describes how to configure the initial mode of operation.
Note:
The HPD pin is also a dedicated configuration pin. HPD forces the entire device to power down except for
the management interface. The Hardware Power-Down mode is described in Section 3.7.3, "Hardware
Power-Down," on page 23.
 2009-2015 Microchip Technology Inc.
DS00001870B-page 23