LAN8810 Datasheet, PDF (68/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
5.5.4 RESET TIMING
Figure 5-4 illustrates the nRESET pin timing requirements. For proper operation, nRESET must be asserted for no less
than t_rstia. In order for valid configuration strap values to be read upon a nRESET assertion, the t_css and t_csh timing con-
straints must be followed. In order for CONFIG[3:0] values to be read at power-up, the t_cs and t_ch timing constraints must
be followed. Refer to Section 3.6.1, "Hardware Reset (nRESET)," on page 22 for additional information.
Note: A hardware reset (nRESET assertion) is required following power-up. Refer to Section 5.5.3, "Power-On
Hardware Reset Timing," on page 67 for additional information.
FIGURE 5-4:
RESET TIMING
nRESET
Configuration
Straps
Configuration Strap
Pins Output Drive
CONFIG[3:0]
t_rstia
t_css
t_csh
t_otaa
t_odad
t_cs
t_ch
TABLE 5-13: RESET TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
t_rstia
t_css
t_csh
t_otaa
t_odad
t_cs
t_ch
nRESET input assertion time
1
Configuration strap pins setup to nRESET deassertion 200
Configuration strap pins hold after nRESET deassertion 10
Output tri-state after nRESET assertion
Output drive after deassertion
40
CONFIG[3:0] setup to nRESET deassertion
0
CONFIG[3:0] hold after nRESET deassertion
1
S
nS
nS
50
nS
800
nS
nS
uS
Note:
Device configuration straps are latched as a result of nRESET assertion. Refer to Section 3.8.1.1, "Con-
figuration Straps," on page 24 details. Configuration straps must only be pulled high or low and must not
be driven as inputs.
5.5.5 GMII TIMING (1000BASE-T)
This section specifies the GMII interface transmit and receive timing. Please refer to Section 3.3, "GMII Interface," on
page 18 for additional details.
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DS00001870B-page 68