LAN8810 Datasheet, PDF (59/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
Bits
Description
15:0 TXPKT[31:16]
Counts the number of transmitted packets.
Contains the 16 middle bits of the 48-bit counter.
Type
RO
Default
0000h
Note:
The 48-bit transmit packet counter is split across 3 registers. In order to read the counter correctly, the reg-
isters must be read in the following order: Transmit Packet Counter Low Register, Transmit Packet Counter
Mid Register, Transmit Packet Counter High Register. After reading the high register, the counter will be
automatically cleared.
4.3.14 TRANSMIT PACKET COUNTER LOW REGISTER
Index:
U12
Size:
16 bits
Bits
Description
15:0 TXPKT[15:0]
Counts the number of transmitted packets.
Contains the 16 low-order bits of the 48-bit counter.
Type
RO
Default
0000h
Note:
The 48-bit transmit packet counter is split across 3 registers. In order to read the counter correctly, the reg-
isters must be read in the following order: Transmit Packet Counter Low Register, Transmit Packet Counter
Mid Register, Transmit Packet Counter High Register. After reading the high register, the counter will be
automatically cleared.
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DS00001870B-page 58