LAN8810 Datasheet, PDF (57/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
4.3.7 CRC ERROR COUNTER HIGH REGISTER
Index:
U5
Size:
16 bits
Bits
Description
15:0 CRCERR[47:32]
Counts the CRC errors, which are generated by the CRC checker circuit.
Contains the 16 upper bits of the 48-bit counter.
Reading this register resets all bits in the CRC Error Counter.
Type
RO/
RC
Default
0000h
Note:
The 48-bit CRC error counter is split across 3 registers. In order to read the counter correctly, the registers
must be read in the following order: , CRC Error Counter Mid Register, CRC Error Counter High Register.
After reading the high register, the counter will be automatically cleared.
4.3.8 CRC ERROR COUNTER MID REGISTER
Index:
U6
Size:
16 bits
Bits
Description
15:0 CRCERR[31:16]
Counts the CRC errors, which are generated by the CRC checker circuit.
Contains the 16 middle bits of the 48-bit counter.
Type
RO
Default
0000h
Note:
The 48-bit CRC error counter is split across 3 registers. In order to read the counter correctly, the registers
must be read in the following order: , CRC Error Counter Mid Register, CRC Error Counter High Register.
After reading the high register, the counter will be automatically cleared.
4.3.9 CRC ERROR COUNTER LOW REGISTER
Index:
U7
Size:
16 bits
Bits
Description
15:0 CRCERR[15:0]
Counts the CRC errors, which are generated by the CRC checker circuit.
Contains the 16 low-order bits of the 48-bit counter.
Type
RO
Default
0000h
Note:
The 48-bit CRC error counter is split across 3 registers. In order to read the counter correctly, the registers
must be read in the following order: , CRC Error Counter Mid Register, CRC Error Counter High Register.
After reading the high register, the counter will be automatically cleared.
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