LAN8810 Datasheet, PDF (32/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
3.9.10.6 Receive Error During Idle Counter
This 16-bit counter counts the number of errors that occurred during idle. The value is read from the Receive Error
During Idle Counter Register register.
3.9.10.7 Transmitted Packets Counter
This 48-bit counter counts the number of packets that were transmitted. It’s value can be read across 3 advanced reg-
isters: Transmit Packet Counter Low Register, Transmit Packet Counter Mid Register, and Transmit Packet Counter
High Register. The Transmit Packet Counter Low Register latches the two other related counter registers and must
always be read first. The Transmit Packet Counter High Register must be read last, and it will automatically clear the
counter.
DS00001870B-page 32
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