LAN8810 Datasheet, PDF (20/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
3.5 Interrupt Management
The device supports multiple interrupt capabilities which are not a part of the IEEE 802.3 specification. An active low
asynchronous interrupt signal may be generated on the IRQ pin when selected events are detected, as configured by
the Interrupt Mask Register.
To set an interrupt, the corresponding mask bit in the Interrupt Mask Register must be set (see Table 3-3). When the
associated event occurs, the IRQ pin will be asserted. When the corresponding event to deassert IRQ is true, the IRQ
pin will be deasserted. All interrupts are masked following a reset.
Note:
Table 3-3 utilizes register index and bit number referencing in lieu of individual names. For example,
“30.10” is used to reference bit 10 (transmitter elastic buffer overflow interrupt enable) of the Interrupt Mask
Register (register index 30).
TABLE 3-4: INTERRUPT MANAGEMENT TABLE
Mask
Interrupt Source Flag
30.15:11
30.10
30.9
30.8
30.7
29.15:11
29.10
29.9
29.8
29.7
RESERVED
Transmitter Elastic
Buffer Overflow
Transmitter Elastic
Buffer Underflow
Idle Error Count
Overflow
ENERGYON
30.6
29.6
Auto-Negotiation
complete
30.5
29.5
Remote Fault
Detected
30.4
29.4
Link Down
30.3
29.3
RESERVED
30.2
29.2
Parallel Detection
Fault
30.1
29.1
Auto-Negotiation
Page Received
Interrupt Source
-NA-
-NA-
-NA-
10.7:0
-NA-
-NA-
(Note 3-3)
-NA-
(Note 3-3)
Idle Error Count
17.1 ENERGYON
1.5 Auto-Negotiate
Complete
1.4 Remote Fault
1.2 Link Status
-NA-
6.4
-NA-
Parallel
Detection Fault
6.1 Page Received
Event to Assert
IRQ
-NA-
Transmitter Elastic
Buffer Overflow
Transmitter Elastic
Buffer Underflow
Idle Error Count
Overflow
Rising 17.1
(Note 3-2)
Rising 1.5
Rising 1.4
Falling 1.2
-NA-
Rising 6.4
Rising 6.1
Event to Deassert
IRQ
-NA-
Overflow condition
resolved
Underflow condition
resolved
Reading register 10
Falling 17.1 or
Reading register 29
Falling 1.5 or
Reading register 29
Falling 1.4, or
Reading register 1 or
Reading register 29
Reading register 1 or
Reading register 29
-NA-
Falling 6.4 or
Reading register 6, or
Reading register 29 or
Re-AutoNegotiate or
Link down
Falling of 6.1 or
Reading register 6, or
Reading register 29
Re-auto-negotiate, or
Link Down.
Note 3-2
The ENERGYON bit of the 10/100 Mode Control/Status Register (17.1) defaults to “1” after a
hardware reset. If no energy is detected before 256mS, the ENERGYON bit will be cleared. When
ENERGYON is “0” and energy is detected, due to the establishment of a valid link or the PHY auto-
negotiation moving past the ability detect state, the ENERGYON bit will be set and the INT7 bit of
the Interrupt Source Flags Register will assert. If ENERGYON is set and the energy is removed, the
INT7 bit will assert. The ENERGYON bit will clear 256mS after the interrupt. If the PHY is in manual
mode, INT7 will be asserted 256mS after the link is broken. If the PHY is auto-negotiating, INT7 will
be asserted 256mS after the PHY returns to the ability detect state (maximum of 1.5S after the link
DS00001870B-page 20
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