LAN8810 Datasheet, PDF (18/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
3.3 GMII Interface
The device communicates with an external MAC using the Gigabit Media Independent Interface (GMII). The GMII is
compliant with the IEEE 802.3 standard, and provides support for 1000BASE-T, 100BASE-TX, or 10BASE-T operation.
For 1000BASE-T, the MAC generated 125MHz GTXCLK transmit clock is used to synchronize the TXD, TXEN and
TXER signals. For 100BASE-TX and 10BASE-T operation, the device generated TXCLK transmit clock is used to syn-
chronize the TXD, TXEN and TXER signals. TXCLK is 25MHz or 2.5MHz for 100BASE-TX and 10BASE-T operation,
respectively. TXER and TXEN are both driven by the MAC and indicate a transmit error and valid transmit data, respec-
tively. On the receiver side, the device generated RXCLK is used to synchronize the RXD, RXDV, RXER, COL and CRS
signals for all modes of operation.
The GMII provides backwards compatibility with the legacy MII. Table 3-3, "GMII/MII Signal Mapping" describes which
pins are used in each mode.
TABLE 3-3: GMII/MII SIGNAL MAPPING
GMII Mode
(IEEE 802.3 Clause 35)
TXD[3:0]
TXD[7:4]
TXEN
TXER
TXCLK (10/100Mbps operation)
GTXCLK (1000Mbps operation)
COL
CRS
RXD[3:0]
RXD[7:4]
RXDV
RXER
RXCLK
MII Mode
(IEEE 802.3 Clause 22)
TXD[3:0]
TXEN
TXER
TXCLK
COL
CRS
RXD[3:0]
RXDV
RXER
RXCLK
Timing information for the GMII/MII interface is provided in Section 5.5, "AC Specifications," on page 65. For additional
information on the GMII/MII interface, refer to the IEEE 802.3 specification.
3.3.1 MII ISOLATE MODE
The device may be configured to electrically isolate the GMII pins by setting the Isolate bit of the Basic Control Register.
In this mode, all MAC data interface output pins are HIGH and all MAC data interface input pins are ignored. In this
mode, the SMI interface is kept active, allowing the MAC to access the SMI registers and generate interrupts. All MDI
operations are halted while in isolate mode.
DS00001870B-page 18
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