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LAN8810 Datasheet, PDF (67/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver
LAN8810/LAN8810I
5.5.3 POWER-ON HARDWARE RESET TIMING
Figure 5-3 illustrates the nRESET, configuration strap/pin, and CONFIG[3:0] timing requirements in relation to power-
on. A hardware reset (nRESET assertion) is required following power-up. For proper operation, nRESET must be
asserted for no less than trstia. The nRESET pin can be asserted at any time, but must not be deasserted before tpurstd
after all external power supplies have reached operational levels. In order for valid configuration strap values to be read
at power-up, the tcss and tcsh timing constraints must be followed. In order for CONFIG[3:0] values to be read at power-
up, the tcs and tch timing constraints must be followed. Refer to Section 3.6.1, "Hardware Reset (nRESET)," on page 22
for additional information.
FIGURE 5-3:
HARDWARE RESET TIMING
All External
Vopp
Power Supplies
nRESET
tpurstv
tpurstd
trstid
Configuration
Straps
Configuration Strap
Pins Output Drive
CONFIG[3:0]
trstia
tcss
tcsh
totaa
todad
tcs
tch
.
TABLE 5-12: HARDWARE RESET TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tpurstd
tpurstv
trstid
trstia
tcss
tcsh
totaa
todad
tcs
tch
External power supplies at operational level to nRESET
25
deassertion
External power supplies at operational level to nRESET
0
valid
nRESET input deassertion time
10
nRESET input assertion time
100
Configuration strap pins setup to nRESET deassertion 200
Configuration strap pins hold after nRESET deassertion 10
Output tri-state after nRESET assertion
Output drive after deassertion
40
CONFIG[3:0] setup to nRESET deassertion
0
CONFIG[3:0] hold after nRESET deassertion
1
mS
nS
S
S
nS
nS
50
nS
800
nS
nS
uS
Note 1: Device configuration straps are latched as a result of nRESET assertion. Refer to Section 3.8.1.1, "Config-
uration Straps," on page 24 details. Configuration straps must only be pulled high or low and must not be
driven as inputs.
2: nRESET deassertion must be monotonic.
DS00001870B-page 67
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