LAN8810 Datasheet, PDF (4/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
1.0 INTRODUCTION
The LAN8810/LAN8810i is a low-power 10BASE-T/100BASE-TX/1000BASE-T Gigabit Ethernet physical layer (PHY)
transceiver with variable I/O voltage that is fully compliant with the IEEE 802.3 and 802.3ab standards.
The LAN8810/LAN8810i can be configured to communicate with an Ethernet MAC via the standard MII(IEEE 802.3u)/
GMII(IEEE 802.3z) interfaces. It contains a full-duplex transceiver for 1000Mbps operation on four pairs of category 5
or better balanced twisted pair cable. Per IEEE 802.3-2005 standards, all digital interface pins are tolerant to 3.6V.
The LAN8810/LAN8810i is configurable via hardware and software, supporting both IEEE 802.3-2005 compliant and
vendor-specific register functions via SMI. The LAN8810/LAN8810i implements Auto-Negotiation to automatically
determine the best possible speed and duplex mode of operation. HP Auto-MDIX support allows the use of direct con-
nect or cross-over cables.
An internal block diagram of the LAN8810/LAN8810i is shown in Figure 1-1. A typical system-level diagram is shown in
Figure 1-2.
FIGURE 1-1:
INTERNAL BLOCK DIAGRAM
LEDs
PLL
LEDs
3
Digital TX ₂
Scrambler
Trellis
1
4DPAM-5 Encoders
0
3
2
1
0
Spectral
Shaper
GMII
Physical
Coding
Sublayer
JTAG
TAP
Controller
Digital RX
Descrambler
Viterbi Decoder
4DPAM-5 Decoders
3
3
2
2
1
10
0 ^DSP
3
3
2
2
1
10
Analog
0
TX
3
3
2
2
1
10
Analog
0 RX
3
2
1
0
3
2
1
0
Active
Hybrid
3210
10/100/1000
Ethernet
LAN8810/LAN8810i
FIGURE 1-2:
SYSTEM LEVEL BLOCK DIAGRAM
Crystal
10/100/1000 ^GMII
Ethernet MAC
LAN8810/
LAN8810i
MDI _Ethernet Ethernet
Magnetics
JTAG
LED
Status
 2009-2015 Microchip Technology Inc.
DS00001870B-page 4