LAN8810 Datasheet, PDF (55/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

4.3.3 USER STATUS 2 REGISTER
Index:
U1
LAN8810/LAN8810I
Size:
16 bits
Bits
Description
15 XOVER Resolution 0:1
0 = Channel 0 and Channel 1 resolved as MDI.
1 = Channel 0 and Channel 1 resolved as MDI-X.
14 XOVER Resolution 2:3
0 = Channel 2 and Channel 3 resolved as MDI.
1 = Channel 2 and Channel 3 resolved as MDI-X.
13 Speed Optimize Status
When set, indicates the link was established using the Speed Optimize
mechanism.
Note: Refer to Section 3.9.5, "Speed Optimizer," on page 29 for additional
information.
12:0 RESERVED
Type
RO
RO
RO
RO
Default
0b
0b
0b
-
4.3.4 RECEIVE ERROR-FREE PACKETS COUNTER HIGH REGISTER
Index:
U2
Size:
16 bits
Bits
Description
15:0 RCVGPKT[47:32]
Counts the received error-free packets.
Contains the 16 upper bits of the 48-bit counter.
Reading this register resets all bits in the Receive Error-Free Packets
Counter.
Type
RO/
RC
Default
0000h
Note:
The 48-bit receive error-free packets counter is split across 3 registers. In order to read the counter cor-
rectly, the registers must be read in the following order: Receive Error-Free Packets Counter Low Register,
Receive Error-Free Packets Counter Mid Register, Receive Error-Free Packets Counter High Register.
After reading the high register, the counter will be automatically cleared.
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DS00001870B-page 54