LAN8810 Datasheet, PDF (45/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

4.2.12 EXTENDED STATUS REGISTER
Index (In Decimal): 15
LAN8810/LAN8810I
Size:
16 bits
Bits
Description
15 1000BASE-X Full Duplex
0 = PHY not able to perform full duplex 1000BASE-X
1 = PHY able to perform full duplex 1000BASE-X
14 1000BASE-X Half Duplex
0 = PHY not able to perform half duplex 1000BASE-X
1 = PHY able to perform half duplex 1000BASE-X
13 1000BASE-T Full Duplex
0 = PHY not able to perform full duplex 1000BASE-T
1 = PHY able to perform full duplex 1000BASE-T
12 1000BASE-T Half Duplex
0 = PHY not able to perform half duplex 1000BASE-T
1 = PHY able to perform half duplex 1000BASE-T
11:0 RESERVED
4.2.13 LINK CONTROL REGISTER
Index (In Decimal): 16
Size:
Type
RO
Default
0b
RO
0b
RO
1b
RO
1b
RO
-
16 bits
Bits
Description
15:10 RESERVED
9:8 Speed Optimize Control
This register sets the number of Auto Negotiation attempts before the Speed
Optimize mechanism reduces the advertised speed.
00 = 7 attempts
01 = 5 attempts
10 = 4 attempts
11 = 3 attempts
Note: Refer to Section 3.9.5, "Speed Optimizer," on page 29 for additional
information.
7:6 RESERVED
5:4 Link Break Threshold
Idle error threshold for failing the link, if Link break in enabled.
00 = link break threshold is 10E-8.
01 = link break threshold is 10E-9.
10 = link break threshold is 10E-10.
11 = link break threshold is 10E-11
3
Link Break Enable
0 = link break is disabled
1 = link break is enabled
Type
RO
R/W
RO
R/W
R/W
Default
-
00b
-
10b
0b
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DS00001870B-page 44