LAN8810 Datasheet, PDF (25/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
Section 3.8.1.2.3 describes how the MOD field controls other configuration bits in the device. When a soft reset is issued
via the PHY Soft Reset (RESET) bit of the Basic Control Register, configuration is controlled by the register bit values
and the CONFIG[3:0] pins have no affect. Likewise, changing the MOD field of the Extended Mode Control/Status Reg-
ister bits does not change the configuration of the device in this case.
Note: Table 3-8 utilizes register index and bit number referencing in lieu of individual names.
TABLE 3-9: CONFIGURING THE MODE OF OPERATION
Mode Definitions
10BASE-T Half Duplex. Auto-negotiation disabled.
10BASE-T Full Duplex. Auto-negotiation disabled.
100BASE-TX Half Duplex. Auto-negotiation disabled.
CRS is active during Transmit & Receive.
100BASE-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
All mode capable (10/100/1000). Auto-negotiation enabled.
Auto master/slave resolution single port.
10BASE-T/100BASE-TX capable. Auto-negotiation enabled.
All mode capable (10/100/1000). Auto-negotiation enabled.
Manual master/slave resolution slave port.
All mode capable (10/100/1000). Auto-negotiation enabled.
Manual master/slave resolution master port.
CONFIG3
CPV(2)
CONFIG2
CPV(0)
CPV(2)
CPV(1)
CPV(2)
CPV(2)
CPV(2)
CPV(3)
CPV(3)
CPV(3)
CPV(3)
CPV(3)
CPV(0)
CPV(1)
CPV(2)
CPV(3)
Reg 19
[15:11]
00000
00001
00010
00011
00111
00100
01001
01010
3.8.1.2.3
Configuration Bits Impacted by the Mode of Operation
Immediately after a reset, the MOD field of the Extended Mode Control/Status Register will be set dependent on the
configuration pin values of the CONFIG3 and CONFIG2 pins, as described in Section 3.8.1.2.2. Table 3-9 details how
the MOD field effects other device configuration register bits.
Note: Table 3-9 utilizes register index and bit number referencing in lieu of individual names
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DS00001870B-page 25