LAN8810 Datasheet, PDF (21/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
Note 3-3
is broken). To prevent an unexpected assertion of IRQ, the ENERGYON interrupt mask (INT7_EN)
should always be cleared as part of the ENERGYON interrupt service routine.
The transmitter FIFO depth can be adjusted via the Transmitter FIFO Depth field of the Extended
Mode Control/Status Register (19.10:9).
3.6 Resets
The device provides the following chip-level reset sources:
• Hardware Reset (nRESET)
• Software Reset
• Power-Down Reset
3.6.1 HARDWARE RESET (NRESET)
Note:
System implementers should connect the nRESET input pin to an output pin from the respective MAC or
microcontroller, so that the required power-up sequence can be performed without causing a full system
reset event.
A hardware reset will occur when the system reset nRESET input pin is driven low. Anytime nRESET is asserted, it must
be held low for the minimum time specified in Section 5.5.4, "Reset Timing," on page 68 to ensure proper reset to the
PHY. Following a hardware reset, the device resets the device registers and relatches the configuration straps and CON-
FIG[3:0] pins.
On first power-up of the device, the sequence below must be also be followed to ensure the device exits reset in the
correct operational state:
1. Perform a hardware reset on power-up as per Section 5.5.3, "Power-On Hardware Reset Timing," on page 67.
2. Wait a minimum of 250mS
3. Write SMI Register 0 (Basic Control Register) = 0x4040
4. Wait a minimum of 1 second
5. Assert the nRESET input pin (nRESET = 0)
6. Wait a minimum of 50mS
7. Deassert the nRESET input pin (nRESET = 1)
After completing this sequence, the LAN8810/LAN8810i will be in the default states and ready for any initialization or
configuration and allow operation.
Note: A hardware reset (nRESET assertion) is required following power-up. Refer to Section 5.5.3, "Power-On
Hardware Reset Timing," on page 67 for additional information.
3.6.2 SOFTWARE RESET
A software reset is initiated by writing a ‘1’ to the PHY Soft Reset (RESET) bit of the Basic Control Register. This self-
clearing bit will return to ‘0’ after approximately 256s, at which time the PHY reset is complete. This reset initializes the
logic within the PHY, with the exception of register bits marked as “NASR” (Not Affected by Software Reset).
Following a software reset, the device configuration is reloaded from the register bit values, and not from the configura-
tion straps and CONFIG[3:0] pins. The device does not relatch the hardware configuration settings. For example, if the
device is powered up and a configuration strap is changed from its initial power up state, a software reset will not load
the new strap setting.
 2009-2015 Microchip Technology Inc.
DS00001870B-page 21