LAN8810 Datasheet, PDF (31/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
The implemented IEEE 1149.1 instructions and their op codes are shown in Table 3-11.
TABLE 3-14: IEEE 1149.1 OP CODES
INSTRUCTION
Bypass
Sample/Preload
EXTEST
Clamp
HIGHZ
IDCODE
OP CODE
111
010
000
011
100
001
COMMENT
Mandatory Instruction
Mandatory Instruction
Mandatory Instruction
Optional Instruction
Optional Instruction
Optional Instruction
Note: All digital I/O pins support IEEE 1149.1 operation. Analog pins and the XO pin do not support IEEE 1149.1
operation.
3.9.10 ADVANCED FEATURES
The device implements several advanced features to enhance manageability of the Ethernet link. These features are
detailed in the following sub-sections.
3.9.10.1 Crossover Indicators
The device reports crossed channels in the XOVER Resolution 0:1 and XOVER Resolution 2:3 fields of the User Status
2 Register. This feature is useful for trouble-shooting problems during network installation.
3.9.10.2 Polarity Inversion Indicators
The device automatically detects and corrects inverted signal polarity. This is reported in the polarity inversion bits
(POLARITY_INV_3, POLARITY_INV_2, POLARITY_INV_1 and POLARITY_INV_0) of the User Status 1 Register.
The polarity inversion bit for Channel 1 (POLARITY_INV_1) is valid after auto-negotiation is complete as indicated by
the Auto-Negotiate Complete bit of the Basic Status Register. The polarity inversion bits for Channels 0, 2 and 3
(POLARITY_INV_0, POLARITY_INV_2, POLARITY_INV_3) are valid only after the link is up as indicated by the Link
Status bit of the Basic Status Register.
3.9.10.3 Receive Error-Free Packets Counter
The quality of a link can be monitored by using the Receive Error-Free Packets Counter. The device counts the number
of good packets received and reports a 48-bit value across 3 advanced registers: Receive Error-Free Packets Counter
Low Register, Receive Error-Free Packets Counter Mid Register, and Receive Error-Free Packets Counter High Reg-
ister. The Receive Error-Free Packets Counter Low Register latches the two other related counter registers and must
always be read first. The Receive Error-Free Packets Counter High Register register must be read last, and will auto-
matically clear the counter.
3.9.10.4 CRC Error Counter
This 48-bit counter counts the number of CRC errors detected. It’s value can be read across 3 advanced registers: CRC
Error Counter Low Register, CRC Error Counter Mid Register, and CRC Error Counter High Register. The CRC Error
Counter Low Register latches the two other related counter registers and must always be read first. The CRC Error
Counter High Register must be read last, and will automatically clear the counter.
3.9.10.5 Receive Error During Data Counter
This 16-bit counter counts the number of errors that occurred while data was being received. The value is read from the
Receive Error During Data Counter Register.
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DS00001870B-page 31