LAN8810 Datasheet, PDF (69/83 Pages) Microchip Technology – GMII 10/100/1000 Ethernet Transceiver

LAN8810/LAN8810I
Note: All GMII timing specifications assume a point-to-point test circuit as defined in Section 35.4.2.2 of the IEEE
802.3-2005 specification.
FIGURE 5-5:
GMII TRANSMIT TIMING
GTXCLK
TXD[7:0],
TXEN, TXER
t_r
t_f
t_val t_hold
t_clkp
t_clkh t_clkl
TABLE 5-14: GMII TRANSMIT TIMING VALUES
Symbol
f_gtxclk
t_clkp
t_clkh
t_clkl
t_val
t_hold
t_r
t_f
Note 5-1
Note 5-2
Description
GTXCLK Frequency
GTXCLK period
GTXCLK high time
GTXCLK low time
TXD[7:0], TXEN, TXER setup time to rising
edge of GTXCLK
TXD[7:0], TXEN, TXER hold time after rising
edge of GTXCLK
GTXCLK rise time
GTXCLK fall time
Min
125 -
100ppm
7.5
2.5
2.5
2.0
Max
125 +
100ppm
8.5
0.0
1
1
Min/max limits are non-sustainable long term.
t_r and t_f are measured from V_{IL_AC(Max)}=0.7V to V_{IH_AC(Min)}=1.9V.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
Notes
Note 5-1
Note 5-2
Note 5-2
DS00001870B-page 69
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