PIC24FV16KM204 Datasheet, PDF (89/336 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

PIC24FV16KM204 FAMILY
REGISTER 8-1: SR: ALU STATUS REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R-0, HSC
—
—
—
—
—
—
—
DC⁽¹⁾
bit 15
bit 8
R/W-0, HSC
IPL2^(2,3)
bit 7
R/W-0, HSC
IPL1^(2,3)
R/W-0, HSC
IPL0^(2,3)
R-0, HSC
RA⁽¹⁾
R/W-0, HSC
N⁽¹⁾
R/W-0, HSC
OV⁽¹⁾
R/W-0, HSC
Z⁽¹⁾
R/W-0, HSC
C⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
HSC = Hardware Settable/Clearable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
bit 7-5
Unimplemented: Read as ‘0’
IPL<2:0>: CPU Interrupt Priority Level Status bits^(2,3)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1:
2:
3:
See Register 3-1 for the description of these bits, which are not dedicated to interrupt control functions.
The IPL<2:0> bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1.
The IPLx Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Note: Bit 8 and bits 4 through 0 are described in Section 3.0 “CPU”.
 2013 Microchip Technology Inc.
Advance Information
DS33030A-page 89