PIC24FV16KM204 Datasheet, PDF (213/336 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

PIC24FV16KM204 FAMILY
REGISTER 19-1: AD1CON1: A/DA/D CONTROL REGISTER 1
R/W-0
ADON
bit 15
U-0
R/W-0
U-0
—
ADSIDL
—
U-0
R/W-0
—
MODE12
R/W-0
FORM1
R/W-0
FORM0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
SSRC3
SSRC2
SSRC1
SSRC0
—
bit 7
R/W-0
ASAM
R/W-0, HSC
SAMP
R/C-0, HSC
DONE
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
HSC = Hardware Settable/Clearable bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9-8
bit 7-4
ADON: A/D Operating Mode bit
1 = A/D Converter module is operating
0 = A/D Converter is off
Unimplemented: Read as ‘0’
ADSIDL: A/D Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
Unimplemented: Read as ‘0’
MODE12: 12-Bit Operation Mode bit
1 = 12-bit A/D operation
0 = 10-bit A/D operation
FORM<1:0>: Data Output Format bits (see the following formats)
11 = Fractional result, signed, left-justified
10 = Absolute fractional result, unsigned, left-justified
01 = Decimal result, signed, right-justified
00 = Absolute decimal result, unsigned, right-justified
SSRC<3:0>: Sample Clock Source Select bits
1111 = Reserved



1101 = Reserved
1100 = CLC2 event ends sampling and starts conversion
1011 = SCCP4 event ends sampling and starts conversion
1010 = MCCP3 event ends sampling and starts conversion
1001 = MCCP2 event ends sampling and starts conversion
1000 = CLC1 event ends sampling and starts conversion
0111 = Internal counter ends sampling and starts conversion (auto-convert)
0110 = TMR1 Sleep mode Trigger event ends sampling and starts conversion⁽¹⁾
0101 = TMR1 event ends sampling and starts conversion
0100 = CTMU event ends sampling and starts conversion
0011 = SCCP5 event ends sampling and starts conversion
0010 = MCCP1 event ends sampling and starts conversion
0001 = INT0 event ends sampling and starts conversion
0000 = Clearing sample bit ends sampling and starts conversion
Note 1: This version of the TMR1 Trigger allows A/D conversions to be triggered from TMR1 while the device is
operating in Sleep mode. The SSRC<3:0> = 0101 option allows conversions to be triggered in Run or Idle
modes only.
 2013 Microchip Technology Inc.
Advance Information
DS33030A-page 213