PIC24FV16KM204 Datasheet, PDF (215/336 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

PIC24FV16KM204 FAMILY
REGISTER 19-2: AD1CON2: A/D CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
U-0
PVCFG1
PVCFG0
NVCFG0
—
BUFREGEN CSCNA
—
bit 15
U-0
—
bit 8
R/W-0
BUFS⁽¹⁾
bit 7
R/W-0
SMPI4
R/W-0
SMPI3
R/W-0
SMPI2
R/W-0
SMPI1
R/W-0
SMPI0
R/W-0
BUFM⁽¹⁾
R/W-0
ALTS
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6-2
bit 1
bit 0
PVCFG<1:0>: Converter Positive Voltage Reference Configuration bits
11 = 4 * Internal VBG⁽²⁾
10 = 2 * Internal VBG⁽³⁾
01 = External VREF+
00 = AVDD
NVCFG0: Converter Negative Voltage Reference Configuration bits
1 = External VREF-
0 = AVSS
Unimplemented: Read as ‘0’
BUFREGEN: A/D Buffer Register Enable bit
1 = Conversion result is loaded into a buffer location determined by the converted channel
0 = A/D result buffer is treated as a FIFO
CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Setting bit
1 = Scans inputs
0 = Does not scan inputs
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit⁽¹⁾
1 = A/D is filling the upper half of the buffer; user should access data in the lower half
0 = A/D is filling the lower half of the buffer; user should access data in the upper half
SMPI<4:0>: Interrupt Sample Rate Select bits
11111 = Interrupts at the completion of the conversion for each 32nd sample
11110 = Interrupts at the completion of the conversion for each 31st sample



00001 = Interrupts at the completion of the conversion for every other sample
00000 = Interrupts at the completion of the conversion for each sample
BUFM: Buffer Fill Mode Select bit⁽¹⁾
1 = Starts filling the buffer at address, AD1BUF0, on the first interrupt and AD1BUF(n/2) on the next
interrupt (Split Buffer mode)
0 = Starts filling the buffer at address, ADCBUF0, and each sequential address on successive
interrupts (FIFO mode)
ALTS: Alternate Input Sample Mode Select bit
1 = Uses channel input selects for Sample A on the first sample and Sample B on the next sample
0 = Always uses channel input selects for Sample A
Note 1:
2:
3:
This is only applicable when the buffer is used in FIFO mode (BUFREGEN = 0). In addition, BUFS is only
used when BUFM = 1.
The voltage reference setting will not be within the specification with VDD below 4.5V.
The voltage reference setting will not be within the specification with VDD below 2.3V.
 2013 Microchip Technology Inc.
Advance Information
DS33030A-page 215