PIC24FV16KM204 Datasheet, PDF (295/336 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

PIC24FV16KM204 FAMILY
FIGURE 27-19: A/D CONVERSION TIMING
BSET AD1CON1, SAMP
BCLR AD1CON1, SAMP
(Note 2)
Q3/Q4
AD58
A/D CLK⁽¹⁾
AD55
AD50
A/D DATA
11 10 9 ^{. . . . . .} 2 1
0
AD59
ADC1BUFn
AD1IF
OLD DATA
NEW DATA
TCY
SAMP
SAMPLING STOPPED
Note 1:
2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.
TABLE 27-38: A/D CONVERSION TIMING REQUIREMENTS⁽¹⁾
AC CHARACTERISTICS
Standard Operating Conditions: 1.8V to 3.6V (PIC24F16KM204)
2.0V to 5.5V (PIC24FV16KM204)
Operating temperature
-40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param
No.
Sym
Characteristic
Min. Typ
Max.
Units
Conditions
Clock Parameters
AD50 TAD A/D Clock Period
600 —
—
ns TCY = 75 ns, AD1CON3 in
default state
AD51 TRC A/D Internal RC Oscillator Period — 1.67
—
µs
Conversion Rate
AD55 TCONV Conversion Time
—
12
—
—
14
—
TAD 10-bit results
TAD 12-bit results
AD56 FCNV Throughput Rate
—
—
100
ksps
AD57 TSAMP Sample Time
—
1
—
TAD
AD58 TACQ Acquisition Time
750 —
—
ns (Note 2)
AD59 TSWC Switching Time from Convert to —
Sample
— (Note 3)
AD60 TDIS Discharge Time
12
—
—
TAD
Clock Parameters
AD61 TPSS Sample Start Delay from
Setting Sample bit (SAMP)
2
—
3
TAD
Note 1:
2:
3:
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD).
On the following cycle of the device clock.
 2013 Microchip Technology Inc.
Advance Information
DS33030A-page 295