PIC24FV16KM204 Datasheet, PDF (243/336 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

PIC24FV16KM204 FAMILY
24.3 Pulse Generation and Delay
The CTMU module can also generate an output pulse
with edges that are not synchronous with the device’s
system clock. More specifically, it can generate a pulse
with a programmable delay from an edge event input to
the module.
When the module is configured for pulse generation
delay by setting the TGEN bit (CTMUCON1L<12>), the
internal current source is connected to the B input of
Comparator 2. A capacitor (CDELAY) is connected to
the Comparator 2 pin, C2INB, and the Comparator
Voltage Reference, CVREF, is connected to C2INA.
CVREF is then configured for a specific trip point. The
module begins to charge CDELAY when an edge event
is detected. While CVREF is greater than the voltage on
CDELAY, CTPLS is high.
When the voltage on CDELAY equals CVREF, CTPLS
goes low. With Comparator 2 configured as the second
edge, this stops the CTMU from charging. In this state
event, the CTMU automatically connects to ground.
The IDISSEN bit doesn’t need to be set and cleared
before the next CTPLS cycle.
Figure 24-3 illustrates the external connections for
pulse generation, as well as the relationship of the
different analog modules required. While CTED1 is
shown as the input pulse source, other options are
available. A detailed discussion on pulse generation
with the CTMU module is provided in the “PIC24F
Family Reference Manual”.
FIGURE 24-3:
TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE
DELAY GENERATION
CTED1
PIC24F Device
CTMU
VDD
EDG1STAT
Current
Source
DQ
CK Q
R
CTPLS
EDG1STAT EDG2STAT
C2INB
CDELAY
Comparator
–
C2
EDG2STAT
CVREF
 2013 Microchip Technology Inc.
Advance Information
DS33030A-page 243