PIC24FV16KM204 Datasheet, PDF (83/336 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

PIC24FV16KM204 FAMILY
7.2.1
POR AND LONG OSCILLATOR
START-UP TIMES
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer (OST) has not
expired (if a crystal oscillator is used).
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system.
Therefore, the oscillator and PLL start-up delays must
be considered when the Reset delay time must be
known.
7.2.2
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
7.3 Special Function Register Reset
States
Most of the Special Function Registers (SFRs)
associated with the PIC24F CPU and peripherals are
reset to a particular value at a device Reset. The SFRs
are grouped by their peripheral or CPU function and their
Reset values are specified in each section of this manual.
The Reset value for each SFR does not depend on the
type of Reset, with the exception of four registers. The
Reset value for the Reset Control register, RCON, will
depend on the type of device Reset. The Reset value for
the Oscillator Control register, OSCCON, will depend on
the type of Reset and the programmed values of the
FNOSCx bits in the Flash Configuration Word
(FOSCSEL<2:0>); see Table 7-2. The RCFGCAL and
NVMCON registers are only affected by a POR.
7.4 Brown-out Reset (BOR)
The PIC24FV16KM204 family devices implement a
BOR circuit, which provides the user several
configuration and power-saving options. The BOR is
controlled by the BORV<1:0> and BOREN<1:0>
Configuration bits (FPOR<6:5,1:0>). There are a total
of four BOR configurations, which are provided in
Table 7-3.
The BOR threshold is set by the BORV<1:0> bits. If
BOR is enabled (any values of BOREN<1:0>, except
‘00’), any drop of VDD below the set threshold point will
reset the device. The chip will remain in BOR until VDD
rises above the threshold.
If the Power-up Timer is enabled, it will be invoked after
VDD rises above the threshold. Then, it will keep the chip
in Reset for an additional time delay, TPWRT, if VDD
drops below the threshold while the Power-up Timer is
running. The chip goes back into a BOR and the
Power-up Timer will be initialized. Once VDD rises above
the threshold, the Power-up Timer will execute the
additional time delay.
BOR and the Power-up Timer (PWRT) are indepen-
dently configured. Enabling the Brown-out Reset does
not automatically enable the PWRT.
7.4.1
LOW-POWER BOR (LPBOR)
The Low-Power BOR is an alternate setting for the BOR,
designed to consume minimal power. In LPBOR mode,
BORV (FPOR<6:5>) = 00. The BOR trip point is approx-
imately 2.0V. Due to the low-current consumption, the
accuracy of the LPBOR mode can vary.
Unlike the other BOR modes, LPBOR mode will not
cause a device Reset when VDD drops below the trip
point. Instead, it re-arms the POR circuit to ensure that
the device will reset properly in the event that VDD
continues to drop below the minimum operating voltage.
The device will continue to execute code when VDD is
below the level of the LPBOR trip point. A device that
requires falling edge BOR protection to prevent code
from improperly executing should use one of the other
BOR voltage settings.
 2013 Microchip Technology Inc.
Advance Information
DS33030A-page 83