PIC24FV16KM204 Datasheet, PDF (41/336 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

PIC24FV16KM204 FAMILY
4.0 MEMORY ORGANIZATION
As with Harvard architecture devices, the PIC24F
microcontrollers feature separate program and data
memory space and busing. This architecture also
allows the direct access of program memory from the
data space during code execution.
4.1 Program Address Space
The program address memory space of the PIC24F
devices is 4M instructions. The space is addressable by
a 24-bit value derived from either the 23-bit Program
Counter (PC) during program execution, or from a table
operation or data space remapping, as described in
Section 4.3 “Interfacing Program and Data Memory
Spaces”.
The user access to the program memory space is
restricted to the lower half of the address range
(000000h to 7FFFFFh). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
Memory maps for the PIC24FV16KM204 family of
devices are displayed in Figure 4-1.
FIGURE 4-1:
PROGRAM SPACE MEMORY MAP FOR PIC24FV16KM204 FAMILY DEVICES
PIC24F08KM
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
Flash
Program Memory
(2816 instructions)
PIC24F16KM
GOTO Instruction
Reset Address
Interrupt Vector Table
Reserved
Alternate Vector Table
000000h
000002h
000004h
0000FEh
000100h
000104h
0001FEh
000200h
User Flash
Program Memory
(5632 instructions)
0015FEh
Unimplemented
Read ‘0’
Data EEPROM
Reserved
Device Config Registers
Reserved
DEVID (2)
Note: Memory areas are not displayed to scale.
Unimplemented
Read ‘0’
Data EEPROM
Reserved
002BFEh
7FFE00h
7FFFFFh
800000h
Device Config Registers
F7FFFEh
F80000h
F80010h
F80012h
Reserved
DEVID (2)
FEFFFEh
FF0000h
FFFFFFh
 2013 Microchip Technology Inc.
Advance Information
DS33030A-page 41