PIC24FV16KM204 Datasheet, PDF(60/336 Page) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

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PIC24FV16KM204 Datasheet, PDF (60/336 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

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TABLE 4-26: CTMU REGISTER MAP

File Name Addr. Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

CTMUCON1L 35Ah CTMUEN

â CTMUSIDL TGEN

EDGEN EDGSEQEN IDISSEN CTTRIG ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0

CTMUCON1H 35Ch EDG1MOD EDG1POL EDG1SEL3 EDG1SEL2 EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT EDG2MOD EDG2POL EDG2SEL3 EDG2SEL2 EDG2SEL1 EDG2SEL0 â

â

CTMUCON2L 35Eh

â

â

â

â

â

â

â

â

â

â

â

IRSTEN

â

DISCHS2 DISCHS1 DISCHS0

Legend: x = unknown, u = unchanged, â = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.

0000

0000

0000

TABLE 4-27: ANSEL REGISTER MAP

File

Name

Addr.

Bit 15

Bit 14

Bit 13 Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

ANSA

ANSB

ANSC

Legend:

Note 1:

2:

3:

4E0h

â

â

â

â

â

â

â

â

â

â

â

ANSA4(2)

4E2h ANSB15 ANSB14 ANSB13 ANSB12 â

â

ANSB9 ANSB8 ANSB7 ANSB6(2) ANSB5(2) ANSB4

4E4h

â

â

â

â

â

â

â

â

â

â

â

â

x = unknown, u = unchanged, â = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.

Reset value depends on the device type; the PIC24F16KM204 value is shown.

These bits are not implemented in 20-pin devices.

These bits are not implemented in 28-pin devices.

ANSA3

ANSB3(2)

â

ANSA2

ANSB2

ANSC2(2,3)

ANSA1

ANSB1

ANSC1(2,3)

ANSA0

ANSB0

ANSC0(2,3)

001F(1)

F3FF(1)

0007(1)

TABLE 4-28: REAL-TIME CLOCK AND CALENDAR REGISTER MAP

File Name Addr. Bit 15 Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7 Bit 6

ALRMVAL 620h

Alarm Value High Register Window Based on APTR<1:0>

ALCFGRPT 622h ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6

RTCVAL

624h

RTCC Value High Register Window Based on RTCPTR<1:0>

RCFGCAL 626h RTCEN

â RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6

RTCPWC 628h PWCEN PWCPOL PWCCPRE PWCSPRE RTCCLK1 RTCCLK0 RTCOUT1 RTCOUT0

â

â

Legend: x = unknown, u = unchanged, â = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.

Note 1: Values are reset only on a VDD POR event.

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

All

Resets

ARPT5

CAL5

â

ARPT4 ARPT3 ARPT2 ARPT1 ARPT0

CAL4

â

CAL3

â

CAL2

â

CAL1

â

CAL0

â

xxxx

0000(1)

xxxx

0000(1)

0000(1)

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