PIC24FV16KM204 Datasheet, PDF (258/336 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

PIC24FV16KM204 FAMILY
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDT instruction during normal execution
If the WDT is enabled in hardware (FWDTEN<1:0> = 11),
it will continue to run during Sleep or Idle modes. When
the WDT time-out occurs, the device will wake and code
execution will continue from where the PWRSAV
instruction was executed. The corresponding SLEEP or
IDLE bit (RCON<3:2>) will need to be cleared in software
after the device wakes up.
The WDT Flag bit, WDTO (RCON<4>), is not auto-
matically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
25.3.1 WINDOWED OPERATION
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
Configuration bit, WINDIS (FWDT<6>), to ‘0’.
25.3.2 CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN<1:0>
Configuration bits. When both of the FWDTEN<1:0>
Configuration bits are set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN<1:0> Configuration bits have been pro-
grammed to ‘10’. The WDT is enabled in software by
setting the SWDTEN control bit (RCON<5>). The
SWDTEN control bit is cleared on any device Reset.
The software WDT option allows the user to enable the
WDT for critical code segments, and disable the WDT
during non-critical segments, for maximum power
savings. When the FWTEN<1:0> bits are set to ‘01’,
the WDT is only enabled in Run and Idle modes, and is
disabled in Sleep. Software control of the SWDTEN bit
(RCON<5>) is disabled with this setting.
FIGURE 25-2:
WDT BLOCK DIAGRAM
SWDTEN
FWDTEN<1:0>
LPRC Input
All Device Resets
Transition to
New Clock Source
Exit Sleep or
Idle Mode
CLRWDT Instr.
PWRSAV Instr.
Sleep or Idle Mode
LPRC Control
FWPSA
Prescaler
(5-Bit/7-Bit)
WDT
Counter
31 kHz
1 ms/4 ms
WDTPS<3:0>
Postscaler
1:1 to 1:32.768
Wake from Sleep
WDT Overflow
Reset
DS33030A-page 258
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