PIC24FV16KM204 Datasheet, PDF (88/336 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

PIC24FV16KM204 FAMILY
8.3 Interrupt Control and Status
Registers
The PIC24FV16KM204 family of devices implements a
total of 33 registers for the interrupt controller:
• INTCON1
• INTCON2
• IFS0 through IFS6
• IEC0 through IEC6
• IPC0 through IPC7, IPC10, IPC12, IPC15, IPC16,
IPC18 through IPC20 and IPC24
• INTTREG
Global Interrupt Enable (GIE) control functions are
controlled from INTCON1 and INTCON2. INTCON1
contains the Interrupt Nesting Disable (NSTDIS) bit, as
well as the control and status flags for the processor
trap sources. The INTCON2 register controls the exter-
nal interrupt request signal behavior and the use of the
AIV table.
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals, or external signal,
and is cleared via software.
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels.
The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into the Vector
Number (VECNUM<6:0>) and the Interrupt Level
(ILR<3:0>) bit fields in the INTTREG register. The new
Interrupt Priority Level is the priority of the pending
interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence. For
example, the INT0 (External Interrupt 0) is depicted as
having a vector number and a natural order priority of
0. The INT0IF status bit is found in IFS0<0>, the INT0IE
enable bit in IEC0<0> and the INT0IP<2:0> priority bits
are in the first position of IPC0 (IPC0<2:0>).
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers con-
tain bits that control interrupt functionality. The ALU
STATUS Register (SR) contains the IPL<2:0> bits
(SR<7:5>). These indicate the current CPU Interrupt
Priority Level. The user may change the current CPU
Interrupt Priority Level by writing to the IPLx bits.
The CORCON register contains the IPL3 bit, which
together with IPL<2:0>, also indicates the current CPU
Interrupt Priority Level. IPL3 is a read-only bit so that the
trap events cannot be masked by the user’s software.
All Interrupt registers are described in Register 8-1
through Register 8-35, in the following sections.
DS33030A-page 88
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