PIC24FV16KM204 Datasheet, PDF (66/336 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

PIC24FV16KM204 FAMILY
4.3.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into a 16K word page of the program space.
This provides transparent access of stored constant
data from the data space without the need to use
special instructions (i.e., TBLRDL/H).
Program space access through the data space occurs
if the MSb of the data space, EA, is ‘1’, and PSV is
enabled by setting the PSV bit in the CPU Control
(CORCON<2>) register. The location of the program
memory space to be mapped into the data space is
determined by the Program Space Visibility Page
Address register (PSVPAG). This 8-bit register defines
any one of 256 possible pages of 16K words in program
space. In effect, PSVPAG functions as the upper 8 bits
of the program memory address, with the 15 bits of the
EA functioning as the lower bits.
By incrementing the PC by 2 for each program memory
word, the lower 15 bits of data space addresses directly
map to the lower 15 bits in the corresponding program
space addresses.
Data reads from this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 4-7), only the lower 16 bits of the
24-bit program word are used to contain the data. The
upper 8 bits of any program space locations used as
data should be programmed with ‘1111 1111’ or ‘0000
0000’ to force a NOP. This prevents possible issues
should the area of code ever be accidentally executed.
Note: PSV access is temporarily disabled during
Table Reads/Writes.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions will
require one instruction cycle in addition to the specified
execution time. All other instructions will require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
FIGURE 4-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1 and EA<15> = 1:
PSVPAG
00
Program Space
23
15
0 _000000h
Data Space
0000h
Data EA<14:0>
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space....
002BFEh
8000h
800000h
PSV Area
...while the lower 15 bits
of the EA specify an exact
address within the PSV
FFFFh area. This corresponds
exactly to the same lower
15 bits of the actual
program space address.
DS33030A-page 66
Advance Information
 2013 Microchip Technology Inc.