PIC24FV16KM204 Datasheet, PDF (134/336 Pages) Microchip Technology – General Purpose, 16-Bit Flash Microcontroller with XLP Technology Data Sheet

PIC24FV16KM204 FAMILY
10.4 Voltage Regulator-Based
Power-Saving Features
The PIC24FV16KM204 family series devices have a
voltage regulator that has the ability to alter
functionality to provide power savings. The on-chip
regulator is made up of two basic modules: the Voltage
Regulator (VREG) and the Retention Regulator
(RETREG). With the combination of VREG and
RETREG, the following power modes are available:
10.4.1 RUN MODE
In Run mode, the main VREG is providing a regulated
voltage with enough current to supply a device running
at full speed and the device is not in Sleep Mode. The
RETREG may or may not be running, but is unused.
10.4.2 SLEEP MODE
In Sleep mode, the device is in Sleep and the main
VREG is providing a regulated voltage to the core. By
default, in Sleep mode, the regulator enters a
low-power standby state which consumes reduced
quiescent current. The PMSLP bit (RCON<8>) controls
the regulator state in Sleep mode. If the PMSLP bit is
set, the program Flash memory will stay powered on
during Sleep mode and the regulator will stay in its
full-power mode.
10.4.3 RETENTION REGULATOR
The Retention Regulator, sometimes referred to as the
low-voltage regulator, is designed to provide power to
the core at a lower voltage than the standard voltage
regulator, while consuming significantly lower quiescent
current. Refer to Section 27.0 “Electrical Characteris-
tics” for the voltage output range of the RETREG. This
regulator is only used in Sleep mode, and has limited
output current to maintain the RAM and provide power
for limited peripherals, such as the WDT, while the
device is in Sleep. It is controlled by the RETCFG Con-
figuration bit (FPOR<2>) and in firmware by the RETEN
bit (RCON<12>). RETCFG must be programmed (= 0)
and the RETEN bit must be set (= 1) for the Retention
Regulator to be enabled.
10.4.4 RETENTION SLEEP MODE
In Retention Sleep mode, the device is in Sleep and all
regulated voltage is provided solely by the RETREG,
while the main VREG is disabled. Consequently, this
mode provides the lowest Sleep power consumption,
but has a trade-off of a longer wake-up time. The
low-voltage Sleep wake-up time is longer than Sleep
mode due to the extra time required to re-enable the
VREG and raise the VDDCORE supply rail back to
normal regulated levels.
Note:
The PIC24FV16KM204 family devices
do not have any internal voltage
regulation, and therefore, do not
support Retention Sleep mode.
TABLE 10-1:
RETCFG Bit
(FPOR<2>)
0
0
0
1
1
VOLTAGE REGULATION CONFIGURATION SETTINGS FOR
PIC24FV16KM204 FAMILY DEVICES
RETEN Bit PMSLP Bit Power Mode
(RCON<12> (RCON<8>) During Sleep
Description
0
1
Sleep
VREG mode (normal) is unchanged during Sleep.
RETREG is unused.
0
0
Sleep
VREG goes to Low-Power Standby mode during
Sleep.
(Standby) RETREG is unused.
1
0
Retention VREG is off during Sleep.
Sleep
RETREG is enabled and provides Sleep voltage
regulation.
x
1
Sleep
VREG mode (normal) is unchanged during Sleep.
RETREG is disabled at all times.
x
0
Sleep
VREG goes to Low-Power Standby mode during
Sleep.
(Standby) RETREG is disabled at all times.
DS33030A-page 134
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