PIC18F2220_07 Datasheet, PDF (41/386 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
TABLE 3-3: ACTIVITY AND EXIT DELAY ON WAKE-UP FROM SLEEP MODE OR
ANY IDLE MODE (BY CLOCK SOURCES)
Clock in
Power-Managed
Mode
Primary System
Clock
Power-Managed
Mode Exit Delay
Clock Ready
Status Bit
(OSCCON)
Activity During Wake-up from
Power-Managed Mode
Exit by Interrupt
Exit by Reset
Primary System
Clock
(PRI_IDLE mode)
LP, XT, HS
HSPLL
EC, RC, INTRC⁽¹⁾
INTOSC⁽²⁾
5-10 μs⁽⁵⁾
OSTS
—
IOFS
CPU and peripherals Not clocked or
clocked by primary clock Two-Speed
and executing
instructions.
Start-up
(if enabled)⁽³⁾.
T1OSC or INTRC⁽¹⁾
INTOSC⁽²⁾
LP, XT, HS
HSPLL
EC, RC, INTRC⁽¹⁾
INTOSC⁽²⁾
LP, XT, HS
HSPLL
EC, RC, INTRC⁽¹⁾
INTOSC⁽²⁾
OST
OST + 2 ms
5-10 μs⁽⁵⁾
1 ms⁽⁴⁾
OST
OST + 2 ms
5-10 μs⁽⁵⁾
None
OSTS
—
IOFS
OSTS
—
IOFS
CPU and peripherals
clocked by selected
power-managed mode
clock and executing
instructions until primary
clock source becomes
ready.
Sleep mode
LP, XT, HS
HSPLL
EC, RC, INTRC⁽¹⁾
INTOSC⁽²⁾
OST
OST + 2 ms
5-10 μs⁽⁵⁾
1 ms⁽⁴⁾
OSTS
—
IOFS
Not clocked or
Two-Speed Start-up (if
enabled) until primary
clock source becomes
ready⁽³⁾.
Note 1: In this instance, refers specifically to the INTRC clock source.
2: Includes both the INTOSC 8 MHz source and postscaler derived frequencies.
3: Two-Speed Start-up is covered in greater detail in Section 23.3 “Two-Speed Start-up”.
4: Execution continues during the INTOSC stabilization period.
5: Required delay when waking from Sleep and all Idle modes. This delay runs concurrently with any other
required delays (see Section 3.3 “Idle Modes”).
© 2007 Microchip Technology Inc.
DS39599F-page 39