PIC18F2220_07 Datasheet, PDF (380/386 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
Resetting, Using a Special Event Trigger
Output (CCP) ................................................... 124
Special Event Trigger (CCP) .................................... 136
TMR1H Register ...................................................... 121
TMR1L Register ....................................................... 121
Use as a Real-Time Clock ....................................... 124
Timer2 .............................................................................. 127
Associated Registers ............................................... 128
Operation ................................................................. 127
Postscaler. See Postscaler, Timer2.
PR2 Register .................................................... 127, 138
Prescaler. See Prescaler, Timer2.
SSP Clock Shift ................................................ 127, 128
TMR2 Register ......................................................... 127
TMR2 to PR2 Match Interrupt .................. 127, 128, 138
Timer3 .............................................................................. 129
Associated Registers ............................................... 131
Operation ................................................................. 130
Oscillator .......................................................... 129, 131
Overflow Interrupt ............................................. 129, 131
Resetting, Using a Special Event Trigger
Output (CCP) ................................................... 131
TMR3H Register ...................................................... 129
TMR3L Register ....................................................... 129
Timing Diagrams
A/D Conversion ........................................................ 340
Acknowledge Sequence ........................................... 188
Asynchronous Reception ......................................... 205
Asynchronous Transmission .................................... 203
Asynchronous Transmission (Back to Back) ............ 203
Baud Rate Generator with Clock Arbitration ............ 182
BRG Reset Due to SDA Arbitration During
Start Condition ................................................. 191
Brown-out Reset (BOR) ........................................... 326
Bus Collision During a Repeated
Start Condition (Case 1) .................................. 192
Bus Collision During a Repeated
Start Condition (Case 2) .................................. 192
Bus Collision During a Stop
Condition (Case 1) ........................................... 193
Bus Collision During a Stop
Condition (Case 2) ........................................... 193
Bus Collision During Start
Condition (SCL = 0) ......................................... 191
Bus Collision During Start
Condition (SDA Only) ....................................... 190
Bus Collision for Transmit and Acknowledge ........... 189
Capture/Compare/PWM (CCP) ................................ 328
CLKO and I/O ........................................................... 325
Clock Synchronization .............................................. 175
Clock, Instruction Cycle .............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 330
Example SPI Master Mode (CKE = 1) ..................... 331
Example SPI Slave Mode (CKE = 0) ....................... 332
Example SPI Slave Mode (CKE = 1) ....................... 333
External Clock (All Modes except PLL) .................... 323
Fail-Safe Clock Monitor (FSCM) .............................. 249
First Start Bit ............................................................ 183
Full-Bridge PWM Output .......................................... 146
Half-Bridge PWM Output .......................................... 145
I²C Bus Data ............................................................ 334
I²C Bus Start/Stop Bits ............................................. 334
I²C Master Mode (Transmission,
7 or 10-bit Address) ......................................... 186
I²C Slave Mode (Transmission, 10-bit Address) ...... 173
I²C Slave Mode (Transmission, 7-bit Address) ........ 171
I²C Slave Mode with SEN = 0 (Reception,
10-bit Address) ................................................ 172
I²C Slave Mode with SEN = 0 (Reception,
7-bit Address) .................................................. 170
I²C Slave Mode with SEN = 1 (Reception,
10-bit Address) ................................................ 177
I²C Slave Mode with SEN = 1 (Reception,
7-bit Address) .................................................. 176
Low-Voltage Detect ................................................. 234
Low-Voltage Detect Characteristics ......................... 320
Master SSP I²C Bus Data ........................................ 336
Master SSP I²C Bus Start/Stop Bits ........................ 336
Parallel Slave Port (PIC18F4X20) ........................... 329
Parallel Slave Port (PSP) Read ............................... 115
Parallel Slave Port (PSP) Write ............................... 115
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 151
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 151
PWM Direction Change ........................................... 148
PWM Direction Change at Near
100% Duty Cycle ............................................. 148
PWM Output ............................................................ 138
Repeat Start Condition ............................................ 184
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST), Power-up Timer (PWRT) ........... 326
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) .............................. 178
Slave Synchronization ............................................. 161
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 51
SPI Mode (Master Mode) ......................................... 160
SPI Mode (Slave Mode with CKE = 0) ..................... 162
SPI Mode (Slave Mode with CKE = 1) ..................... 162
Stop Condition Receive or Transmit Mode .............. 188
Synchronous Transmission ..................................... 206
Synchronous Transmission (Through TXEN) .......... 207
Time-out Sequence on POR w/ PLL
Enabled (MCLR Tied to VDD) ............................ 51
Time-out Sequence on Power-up
(MCLR Not Tied to VDD): Case 1 ....................... 50
Time-out Sequence on Power-up
(MCLR Not Tied to VDD): Case 2 ....................... 50
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise TPWRT) .............. 50
Timer0 and Timer1 External Clock .......................... 327
Transition for Entry to SEC_IDLE Mode .................... 34
Transition for Entry to SEC_RUN Mode .................... 36
Transition for Entry to Sleep Mode ............................ 32
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 247
Transition for Wake from PRI_IDLE Mode ................ 33
Transition for Wake from RC_RUN Mode
(RC_RUN to PRI_RUN) ..................................... 35
Transition for Wake from
SEC_RUN Mode (HSPLL) ................................. 34
Transition for Wake from Sleep (HSPLL) .................. 32
Transition to PRI_IDLE Mode .................................... 33
Transition to RC_IDLE Mode ..................................... 35
Transition to RC_RUN Mode ..................................... 37
USART Synchronous Receive ( Master/Slave) ....... 338
USART Synchronous Reception
(Master Mode, SREN) ..................................... 208
USART SynchronousTransmission (Master/Slave) . 338
DS39599F-page 378
© 2007 Microchip Technology Inc.