PIC18F2220_07 Datasheet, PDF (35/386 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
3.3.1 PRI_IDLE MODE
This mode is unique among the three Low-Power Idle
modes in that it does not disable the primary system
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation, with its
more accurate primary clock source, since the clock
source does not have to “warm up” or transition from
another oscillator.
PRI_IDLE mode is entered by setting the IDLEN bit,
clearing the SCS bits and executing a SLEEP instruc-
tion. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified in Configuration Register 1H. The OSTS bit
remains set in PRI_IDLE mode (see Figure 3-3).
When a wake-up event occurs, the CPU is clocked
from the primary clock source. A delay of approxi-
mately 10 μs is required between the wake-up event
and when code execution starts. This is required to
allow the CPU to become ready to execute instructions.
After the wake-up, the OSTS bit remains set. The
IDLEN and SCS bits are not affected by the wake-up
(see Figure 3-4).
FIGURE 3-3:
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
TRANSITION TIMING TO PRI_IDLE MODE
Q1
Q2
Q3
Q4
Q1
PC
PC + 2
FIGURE 3-4:
TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE
OSC1
CPU Clock
Peripheral
Clock
Program
Counter
CPU Start-up Delay
PC
Wake-up Event
Q1
Q2
Q3
Q4
PC + 2
© 2007 Microchip Technology Inc.
DS39599F-page 33