PIC18F2220_07 Datasheet, PDF (256/386 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
23.5.2 DATA EEPROM
CODE PROTECTION
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits external writes to data EEPROM. The
CPU can continue to read and write data EEPROM
regardless of the protection bit settings.
23.5.3 CONFIGURATION REGISTER
PROTECTION
The configuration registers can be write-protected. The
WRTC bit controls protection of the configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
23.6 ID Locations
Eight memory locations (200000h-200007h) are desig-
nated as ID locations, where the user can store check-
sum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRD and TBLWT instructions,
or during program/verify. The ID locations can be read
when the device is code-protected.
23.7 In-Circuit Serial Programming
PIC18F2X20/4X20 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed (see Table 23-5).
23.8 In-Circuit Debugger
When the DEBUG bit in configuration register,
CONFIG4L, is programmed to a ‘0’, the In-Circuit
Debugger functionality is enabled. This function allows
simple debugging functions when used with MPLAB^®
IDE. When the microcontroller has this feature
enabled, some resources are not available for general
use. Table 23-4 shows which resources are required by
the background debugger.
TABLE 23-4: DEBUGGER RESOURCES
I/O pins:
RB6, RB7
Stack:
Program Memory:
Data Memory:
2 levels
512 bytes
10 bytes
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, VSS,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
23.9 Low-Voltage ICSP Programming
The LVP bit in Configuration Register 4L
(CONFIG4L<2>) enables Low-Voltage ICSP Program-
ming (LVP). When LVP is enabled, the microcontroller
can be programmed without requiring high voltage
being applied to the MCLR/VPP pin, but the RB5/PGM
pin is then dedicated to controlling Program mode entry
and is not available as a general purpose I/O pin.
LVP is enabled in erased devices.
While programming using LVP, VDD is applied to the
MCLR/VPP pin as in normal execution mode. To enter
Programming mode, VDD is applied to the PGM pin.
Note 1: High-voltage programming is always
available, regardless of the state of the
LVP bit or the PGM pin, by applying VIHH
to the MCLR pin.
2: When Low-Voltage Programming is
enabled, the RB5 pin can no longer be
used as a general purpose I/O pin.
3: When LVP is enabled, externally pull the
PGM pin to VSS to allow normal program
execution.
If Low-Voltage ICSP Programming mode will not be
used, the LVP bit can be cleared and RB5/PGM
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (VIHH applied to the MCLR/
VPP pin). Once LVP has been disabled, only the stan-
dard high-voltage programming is available and must
be used to program the device.
Memory that is not code-protected can be erased using
either a block erase, or erased row by row, then written
at any specified VDD. If code-protected memory is to be
erased, a block erase is required. If a block erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with VDD of 4.5V to 5.5V.
TABLE 23-5: ICSP/ICD CONNECTIONS
Signal Pin
Notes
PGD
PGC
MCLR
VDD
VSS
PGM
RB7
RB6
MCLR
VDD
VSS
RB5
May require isolation from
application circuits
Pull RB5 low if LVP is enabled
DS39599F-page 254
© 2007 Microchip Technology Inc.