PIC18F2220_07 Datasheet, PDF (247/386 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
23.2 Watchdog Timer (WDT)
For PIC18F2X20/4X20 devices, the WDT is driven by
the INTRC source. When the WDT is enabled, the
clock source is also enabled. The nominal WDT period
is 4 ms and has the same stability as the INTRC
oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in Configu-
ration Register 2H. Available periods range from 4 ms
to 131.072 seconds (2.18 minutes). The WDT and
postscaler are cleared when any of the following events
occur: execute a SLEEP or CLRWDT instruction, the
IRCF bits (OSCCON<6:4>) are changed or a clock
failure has occurred.
Adjustments to the internal oscillator clock period using
the OSCTUNE register also affect the period of the
WDT by the same factor. For example, if the INTRC
period is increased by 3%, then the WDT period is
increased by 3%.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCF bits
(OSCCON<6:4> clears the WDT and
postscaler counts.
3: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
23.2.1 CONTROL REGISTER
Register 23-14 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
configuration bit, but only if the configuration bit has
disabled the WDT.
FIGURE 23-1:
WDT BLOCK DIAGRAM
SWDTEN
WDTEN
INTRC Source
Change on IRCF bits
CLRWDT
All Device Resets
WDTPS<3:0>
Sleep
Enable WDT
INTRC Control
WDT Counter
÷125
Programmable Postscaler ^Reset
1:1 to 1:32,768
WDT
4
Wake-up
from Sleep
WDT
Reset
© 2007 Microchip Technology Inc.
DS39599F-page 245