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PIC18F2220_07 Datasheet, PDF (12/386 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PIC18F2220/2320/4220/4320
FIGURE 1-2:
PIC18F4220/4320 BLOCK DIAGRAM
Data Bus<8>
21
21
Address Latch
Program Memory
(8 Kbytes)
Data Latch
16
21 Table Pointer <2> 8
8
8
inc/dec logic
20 PCLATU PCLATH
PCU PCH PCL
Program Counter
31 Level Stack
Data Latch
8
Data RAM
(512 Bytes)
Address Latch
12(2)
Address<12>
4
BSR
12
FSR0
FSR1
FSR2
4
Bank0, F
12
Table Latch
inc/dec
Decode logic
8
ROM Latch
OSC1(3)
OSC2(3)
T1OSI
T1OSO
MCLR(2)
VDD, VSS
Instruction
Decode &
Control
Instruction
Register
Internal
Oscillator
Block
INT RC
Oscillator
Low-Voltage
Programming
In-Circuit
Debugger
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
Fail-Safe
Clock Monitor
8
PRODH PRODL
3
8 x 8 Multiply
8
BIT OP WREG
8
8
8
8
ALU<8>
8
Precision
Voltage
Reference
PORTA
PORTB
PORTC
PORTD
PORTE
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
RA5/AN4/SS/LVDIN/C2OUT
OSC2/CLKO/RA6(3)
OSC1/CLKI/RA7(3)
RB0/AN12/INT0
RB1/AN10/INT1
RB2/AN8/INT2
RB3/AN9/CCP2(1)
RB4/AN11/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
RB7/KBI3/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5/P1B
RD6/PSP6/P1C
RD7/PSP7/P1D
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
RE3(2)
Timer0
(8- or 16-bit)
Timer1
(16-bit)
Timer2
(8-bit)
Timer3
(16-bit)
10-bit A/D
Converter
Enhanced
CCP
CCP2
Master
Synchronous
Serial Port
Addressable
USART
Data EEPROM
(256 Bytes)
Note
1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of the CCP2MX configuration bit.
2: RE3 is available only when the MCLR Resets are disabled.
3: OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O.
Refer to Section 2.0 “Oscillator Configurations” for additional information.
DS39599F-page 10
© 2007 Microchip Technology Inc.