PIC18F2220_07 Datasheet, PDF (261/386 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
TABLE 24-2: PIC18FXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
16-Bit Instruction Word
Cycles
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BC
n
BN
n
BNC
n
BNN
n
BNOV
n
BNZ
n
BOV
n
BRA
n
BZ
n
CALL
n, s
CLRWDT —
DAW
—
GOTO
n
NOP
—
NOP
—
POP
—
PUSH
—
RCALL n
RESET
RETFIE s
Branch if Carry
1 (2)
Branch if Negative
1 (2)
Branch if Not Carry
1 (2)
Branch if Not Negative
1 (2)
Branch if Not Overflow
1 (2)
Branch if Not Zero
1 (2)
Branch if Overflow
1 (2)
Branch Unconditionally
2
Branch if Zero
1 (2)
Call subroutine 1st word
2
2nd word
Clear Watchdog Timer
1
Decimal Adjust WREG
1
Go to address 1st word
2
2nd word
No Operation
1
No Operation (Note 4)
1
Pop top of return stack (TOS) 1
Push top of return stack (TOS) 1
Relative Call
2
Software device Reset
1
Return from interrupt enable 2
RETLW k
RETURN s
SLEEP —
Return with literal in WREG 2
Return from Subroutine
2
Go into Standby mode
1
1110 0010
1110 0110
1110 0011
1110 0111
1110 0101
1110 0001
1110 0100
1101 0nnn
1110 0000
1110 110s
1111 kkkk
0000 0000
0000 0000
1110 1111
1111 kkkk
0000 0000
1111 xxxx
0000 0000
0000 0000
1101 1nnn
0000 0000
0000 0000
0000 1100
0000 0000
0000 0000
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
nnnn
kkkk
kkkk
0000
0000
kkkk
kkkk
0000
xxxx
0000
0000
nnnn
1111
0001
kkkk
0001
0000
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
nnnn None
kkkk None
kkkk
0100 TO, PD
0111 C, DC
kkkk None
kkkk
0000 None
xxxx None
0110 None
0101 None
nnnn None
1111 All
000s GIE/GIEH,
PEIE/GIEL
kkkk None
001s None
0011 TO, PD
Note 1: When a Port register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that
value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is
driven low by an external device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared
if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The
second cycle is executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP
unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all
program memory locations have a valid instruction.
5: If the table write starts the write cycle to internal memory, the write will continue until terminated.
© 2007 Microchip Technology Inc.
DS39599F-page 259