PIC18F2220_07 Datasheet, PDF (105/386 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2220/2320/4220/4320
TABLE 10-1: PORTA FUNCTIONS
Name
Bit# Buffer
Function
RA0/AN0
RA1/AN1
RA2/AN2/VREF-/CVREF
RA3/AN3/VREF+
RA4/T0CKI/C1OUT
bit 0 TTL Input/output or analog input.
bit 1 TTL Input/output or analog input.
bit 2 TTL Input/output, analog input, VREF- or Comparator VREF output.
bit 3 TTL Input/output, analog input or VREF+.
bit 4
ST Input/output, external clock input for Timer0 or Comparator 1
output. Output is open-drain type.
RA5/AN4/SS/LVDIN/C2OUT bit 5
TTL Input/output, analog input, Slave Select input for Synchronous
Serial Port, Low-Voltage Detect input or Comparator 2 output.
OSC2/CLKO/RA6
bit 6 TTL OSC2, clock output or I/O pin.
OSC1/CLKI/RA7
bit 7 TTL OSC1, clock input or I/O pin.
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 10-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
PORTA
LATA
TRISA
RA7⁽¹⁾
LATA7⁽¹⁾
TRISA7⁽¹⁾
RA6⁽¹⁾
LATA6⁽¹⁾
TRISA6⁽¹⁾
RA5
RA4
RA3
LATA Data Latch Register
PORTA Data Direction Register
RA2
RA1
RA0 xx0x 0000 uu0u 0000
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
ADCON1
—
—
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --00 0000
CMCON
C2OUT C1OUT C2INV C1INV CIS
CM2
CM1
CM0 0000 0111 0000 0111
CVRCON CVREN CVROE CVRR
—
CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration;
otherwise, they are read as ‘0’.
© 2007 Microchip Technology Inc.
DS39599F-page 103