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PIC18F2220_07 Datasheet, PDF (265/386 Pages) Microchip Technology – 28/40/44-Pin High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology | |||
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PIC18F2220/2320/4220/4320
ANDWF
AND W with f
Syntax:
[ label ] ANDWF f [,d [,a]]
Operands:
0 ⤠f ⤠255
d â [0,1]
a â [0,1]
Operation:
(W) .AND. (f) â dest
Status Affected: N, Z
Encoding:
0001 01da ffff ffff
Description:
The contents of W are ANDâed with
register âfâ. If âdâ is â0â, the result is
stored in W. If âdâ is â1â, the result is
stored back in register âfâ (default).
If âaâ is â0â, the Access Bank will be
selected. If âaâ is â1â, the BSR will
not be overridden (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register âfâ
Q3
Process
Data
Q4
Write to
destination
Example:
ANDWF
Before Instruction
W
REG
= 0x17
= 0xC2
After Instruction
W
REG
= 0x02
= 0xC2
REG, W
BC
Branch if Carry
Syntax:
[ label ] BC n
Operands:
-128 ⤠n ⤠127
Operation:
if carry bit is â1â
(PC) + 2 + 2n â PC
Status Affected: None
Encoding:
1110 0010 nnnn nnnn
Description:
If the Carry bit is â1â, then the
program will branch.
The 2âs complement number â2nâ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then a
two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
No
operation
If No Jump:
Read literal
ânâ
No
operation
Process
Data
No
operation
Write to PC
No
operation
Q1
Q2
Q3
Q4
Decode
Read literal
ânâ
Process
Data
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Carry
=
PC
=
If Carry
=
PC
=
BC JUMP
address (HERE)
1;
address (JUMP)
0;
address (HERE+2)
© 2007 Microchip Technology Inc.
DS39599F-page 263
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