80C286_08 Datasheet, PDF (50/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
Waveforms (Continued)
BUS
CYCLE TYPE
V_CH ^TI φ2
CLK
V_CL
S1 • S0
A23 - A0
M/IO,
COD INTA
12A
PEACK
PEREQ
φ1 ^TS φ2
1
T_C
φ2
φ1 ^TS φ2
φ1 ^TC φ2
φ1
T_I
I/O READ IF PROC. EXT. TO MEMORY
MEMORY READ IF MEMORY TO PROC. EXT.
MEMORY WRITE IF PROC. EXT. TO MEMORY
I/O WRITE IF MEMORY TO PROC. EXT.
12B
(SEE NOTE 54)
(SEE NOTE 55)
4
MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER I/O PORT
ADDRESS 00FA(H) IF MEMORY TO PROC. EXT. TRANSFER
I/O PORT ADDRESS 00FA(H) IF PROC. EXT. TO MEMORY TRANSFER
MEMORY ADDRESS IF MEMORY TO PROC. EXT. TRANSFER
5
ASSUMING WORD-ALIGNED MEMORY OPERAND. IF ODD ALIGNED, 80C286 TRANSFERS TO/FROM MEMORY BYTE-AT-A-TIME WITH TWO MEMORY
CYCLES.
NOTES:
FIGURE 38. 80C286 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY
54. PEACK always goes active during the first bus operation of a processor extension data operand transfer sequence. The first bus opera-
tion will be either a memory read at operand address or I/O read at port address 00FA(H).
55. To prevent a second processor extension data operand transfer, the worst case maximum time (Shown above) is
3 x 1 - 12A_MAX - 4 _MIN. The actual configuration dependent, maximum time is: 3 x 1 - 12A_MAX - 4 _MIN + N x 2 x 1 . N is the
number of extra T_C states added to either the first or second bus operation of the processor extension data operand transfer sequence.
BUS
CYCLE TYPE
V_CH
CLK
V_CL
RESET
S1 • S0
PEACK
A₂₃ - A₀
BHE
M/IO
COD/INTA
LOCK
DATA
HLDA
φ2
T_X
φ1
φ2
φ1 ^TX φ2
φ1 ^TX φ2
φ1 ^TI φ2
19
(SEE NOTE 56)
7
6
AT LEAST
16 CLK PERIODS
12B
(SEE NOTE 57)
UNKNOWN
13
UNKNOWN
UNKNOWN
UNKNOWN
13
13
15
(SEE NOTE 58)
16
UNKNOWN
NOTES:
FIGURE 39. INITIAL 80C286 PIN STATE DURING RESET
56. Setup time for RESET ↑ may be violated with the consideration that φ1 of the processor clock may begin one system CLK period later.
57. Setup and hold times for RESET ↓ must be met for proper operation, but RESET ↓ may occur during φ1 or φ2.
58. The data bus is only guaranteed to be in a high impedance state at the time shown.
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