80C286_08 Datasheet, PDF (49/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

Waveforms (Continued)
80C286
BUS
CYCLE TYPE
V_CH
CLK
V_CL
HLDA
T_H
φ1
φ2
16
T_S OR T_I
φ1
φ2
T_I
φ1
φ2
T_H
φ1
φ2
16
(SEE NOTE 51)
S1 • S0
CLK
BHE, LOCK
A₂₃ - A₀,
M/IO,
COD/INTA
D₁₅ - D₀
12A ^{(SEE NOTE 50)}
12B
IF T_S
(SEE NOTE 52)
IF NPX TRANSFER
13
VALID
14
(SEE NOTE 53)
15 (SEE NOTE 50)
15
(SEE NOTE 48)
15
(SEE NOTE 49)
15
VALID IF WRITE
PCLK
NOTES:
FIGURE 37. EXITING AND ENTERING HOLD
48. These signals may not be driven by the 80C286 during the time shown. The worst case in terms of latest float time is shown.
49. The data bus will be driven as shown if the cycle before T_I in the diagram was a write T_C.
50. The 80C286 puts its status pins in a high impedance logic one state during T_H.
51. For HOLD request set up to HLDA, refer to Figure 29.
52. BHE and LOCK are driven at this time but will not become valid until T_S.
53. The data bus will remain in a high impedance state if a read cycle is performed.
49