80C286_08 Datasheet, PDF (37/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
Local Bus Usage Priorities
The 80C286 local bus is shared among several internal units
and external HOLD requests. In case of simultaneous
requests, their relative priorities are:
(Highest)
Any transfers which assert LOCK either explic-
itly (via the LOCK instruction prefix) or implic-
itly (i.e. some segment descriptor accesses, an
interrupt acknowledge sequence, or an XCHG
with memory).
The second of the two byte bus operations
required for an odd aligned word operand.
The second or third cycle of a processor exten-
sion data transfer.
Local bus request via HOLD input.
Processor extension data operand transfer via
PEREQ input.
Data transfer performed by EU as part of an
instruction.
(Lowest)
An instruction prefetch request from BU. The
EU will inhibit prefetching two processor clocks
in advance of any data transfers to minimize
waiting by the EU for a prefetch to finish.
Halt or Shutdown Cycles
The 80C286 externally indicates halt or shutdown conditions
as a bus operation. These conditions occur due to a HLT
instruction or multiple protection exceptions while attempting
to execute one instruction. A halt or shutdown bus operation
is signalled when S₁, S₀ and COD/lNTA are LOW and M/IO
is HIGH. A₁ HIGH indicates halt, and A₁ LOW indicates
shutdown. The 82C288 bus controller does not issue ALE,
nor is READY required to terminate a halt or shutdown bus
operation.
During halt or shutdown, the 80C286 may service PEREQ or
HOLD requests. A processor extension segment overrun
during shutdown will inhibit further service of PEREQ. Either
NMl or RESET will force the 80C286 out of either halt or
shutdown. An INTR, if interrupts are enabled, or a processor
extension segment overrun exception will also force the
80C286 out of halt.
System Configurations
The versatile bus structure of the 80C286 micro-system, with
a full complement of support chips, allows flexible configura-
tion of a wide range of systems. The basic configuration,
shown in Figure 30, is similar to an 80C86 maximum mode
system. It includes the CPU plus an 82C59A interrupt con-
troller, 82C284 clock generator, and the 82C288 Bus Con-
troller. The 80C86 latches (82C82 and 82C83H) and
transceivers (82C86H and 82C87H) may be used in an
80C286 microsystem.
As indicated by the dashed lines in Figure 30, the ability to
add processor extensions is an integral feature of 80C286
based microsystems. The processor extension interface
allows external hardware to perform special functions and
transfer data concurrent with CPU execution of other instruc-
tions. Full system integrity is maintained because the
80C286 supervises all data transfers and instruction execu-
tion for the processor extension.
An 80C286 system which includes the 80287 numeric proces-
sor extension (NPX) uses this interface. The 80C286/80287
system has all the instructions and data types of an 80C86 or
80C88 with 8087 numeric processor extension. The 80287
NPX can perform numeric calculations and data transfers
concurrently with CPU program execution. Numerics code
and data have the same integrity as all other information pro-
tected by the 80C286 protection mechanism.
The 80C286 can overlap chip select decoding and address
propagation during the data transfer for the previous bus
operation. This information is latched into the 82C82/83H's
by ALE during the middle of a T_S cycle. The latched chip
select and address information remains stable during the
bus operation while the next cycle's address is being
decoded and propagated into the system. Decode logic can
be implemented with a high speed PROM or PAL.
The optional decode logic shown in Figure 30 takes advan-
tage of the overlap between address and data of the 80C286
bus cycle to generate advanced memory and I/O select sig-
nals. This minimizes system performance degradation
caused by address propagation and decode delays. In addi-
tion to selecting memory and I/O, the advanced selects may
be used with configurations supporting local and system
buses to enable the appropriate bus interface for each bus
cycle. The COD/lNTA and M/IO signals are applied to the
decode logic to distinguish between interrupt, I/O, code, and
data bus cycles.
By adding the 82289 bus arbiter chip the 80C286 provides a
Multibus system bus interface as shown in Figure 31. The
ALE output of the 82C288 for the Multibus bus is connected to
its CMDLY input to delay the start of commands one system
CLK as required to meet Multibus address and write data
setup times. This arrangement will add at least one extra T_C
state to each bus operation which uses the Multibus.
A second 82C288 bus controller and additional latches and
transceivers could be added to the local bus of Figure 31.
This configuration allows the 80C286 to support an on-board
bus for local memory and peripherals, and the Multibus for
system bus interfacing.
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