80C286_08 Datasheet, PDF (15/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
TABLE 8. RECOMMENDED MSW ENCODINGS FOR PROCESSOR EXTENSION CONTROL
TS
MP
EM
RECOMMENDED USE
INSTRUCTION
CAUSING
EXCEPTION 7
0
0
0
Initial encoding after RESET. 80C286 operation is identical to 80C86/88.
None
0
0
1
No processor extension is available. Software will emulate its function.
ESC
1
0
1
No processor extension is available. Software will emulate its function. The
ESC
current processor extension context may belong to another task.
0
1
0
A processor extension exists.
None
1
1
0
A processor extension exists. The current processor extension context may
ESC or WAIT
belong to another task. The exception 7 on WAIT allows software to test for
an error pending from a previous processor extension operation.
TABLE 9. REAL ADDRESS MODE ADDRESSING INTERRUPTS
FUNCTION
Interrupt table limit too small exception
Processor extension segment overrun
interrupt
Segment overrun exception
INTERRUPT
NUMBER
RELATED INSTRUCTIONS
RETURN ADDRESS
BEFORE INSTRUCTION
8
INT vector is not within table limit
Yes
9
ESC with memory operand extending beyond offset
No
FFFF(H)
13
Word memory reference with offset = FFFF(H) or an
Yes
attempt to execute past the end of a segment
80C286 Real Address Mode
The 80C286 executes a fully upward-compatible superset of
the 80C86 instruction set in real address mode. In real
address mode the 80C286 is object code compatible with
80C86 and 80C88 software. The real address mode archi-
tecture (registers and addressing modes) is exactly as
described in the 80C286 Base Architecture section of this
Functional Description.
in a segment does not use the full 64K bytes, the unused
end of the segment may be overlaid by another segment to
reduce physical memory requirements.
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0000
OFFSET
0
OFFSET
ADDRESS
Memory Size
Physical memory is a contiguous array of up to 1,048,576
bytes (one megabyte) addressed by pins A₀ through A₁₉
and BHE. A₂₀ through A₂₃ should be ignored.
Memory Addressing
In real address mode physical memory is a contiguous array
of up to 1,048,576 bytes (one megabyte) addressed by pin
A₀ through A₁₉ and BHE. Address bits A₂₀-A₂₃ may not
always be zero in real mode. A₂₀-A₂₃ should not be used by
the system while the 80C286 is operating in Real Mode.
The selector portion of a pointer is interpreted as the upper
16-bits of a 20-bit segment address. The lower four bits of
the 20-bit segment address are always zero. Segment
addresses, therefore, begin on multiples of 16 bytes. See
Figure 6 for a graphic representation of address information.
All segments in real address mode are 64K bytes in size and
may be read, written, or executed. An exception or interrupt
can occur if data operands or instructions attempt to wrap
around the end of a segment (e.g. a word with its low order
byte at offset FFFF(H) and its high order byte at offset
0000(H)). If, in real address mode, the information contained
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SEGMENT
SELECTOR
0
0000
SEGMENT
ADDRESS
ADDER
19
0
20-BIT PHYSICAL
MEMORY ADDRESS
FIGURE 6. 80C286 REAL ADDRESS MODE ADDRESS
CALCULATION
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