80C286_08 Datasheet, PDF (29/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
T_I
CLK
PROC
CLK
A₂₃ - A₀
READ BUS CYCLE N
T_S
T_C
φ1
φ2
φ1
φ2
READ BUS CYCLE N + 1
T_S
T_C
φ1
φ2
φ1
φ2
2 PCLK CYCLE TRANSFER
VALID ADDR (N)
2 PCLK CYCLE TRANSFER
2.5 CLOCK CYCLE ADDRESS TO DATA VALID
VALID ADDR (N + 1)
S0 • S1
READY
D₁₅ - D₀
VALID READ
DATA (N)
PIPELINING: VALID ADDRESS (N + 1) AVAILABLE IN LAST PHASE OF BUS CYCLE (N).
FIGURE 22. BASIC BUS CYCLE
VALID READ
DATA (N + 1)
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