80C286_08 Datasheet, PDF(13/60 Page) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

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80C286_08 Datasheet, PDF (13/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

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80C286

TABLE 4. INTERRUPT VECTOR ASSIGNMENTS

FUNCTION

Divide Error Exception

Single Step Interrupt

NMI Interrupt

Breakpoint Interrupt

INTO Detected Overflow Exception

BOUND Range Exceeded Exception

Invalid Opcode Exception

Processor Extension Not Available Exception

Reserved - Do Not Use

Processor Extension Error Interrupt

Reserved

User Defined

INTERRUPT

NUMBER

8 - 15

17 - 31

32 - 255

INSTRUCTIONS

DlV, lDlV

All

INT 2 or NMI Pin

INT 3

INTO

BOUND

Any Undefined Opcode

ESC or WAIT

DOES RETURN ADDRESS

POINT TO INSTRUCTION

CAUSING EXCEPTION?

Yes

I/O Space

The I/O space consists of 64K 8-bit ports, 32K 16-bit ports, or

a combination of the two. I/O instructions address the I/O

space with either an 8-bit port address, specified in the

instruction, or a 16-bit port address in the DX register. 8-bit

port addresses are zero extended such that A15-A8 are LOW.

I/O port addresses 00F8(H) through 00FF(H) are reserved.

Interrupts

An interrupt transfers execution to a new program location.

The old program address (CS:lP) and machine state (Flags)

are saved on the stack to allow resumption of the interrupted

program. Interrupts fall into three classes: hardware initiated,

INT instructions, and instruction exceptions. Hardware initi-

ated interrupts occur in response to an external input and

are classified as non-maskable or maskable. Programs may

cause an interrupt with an INT instruction. Instruction excep-

tions occur when an unusual condition which prevents fur-

ther instruction processing is detected while attempting to

execute an instruction. The return address from an excep-

tion will always point to the instruction causing the exception

and include any leading instruction prefixes.

A table containing up to 256 pointers defines the proper

interrupt service routine for each interrupt. Interrupts 0-31,

some of which are used for instruction exceptions, are

reserved. For each interrupt, an 8-bit vector must be sup-

plied to the 80C286 which identifies the appropriate table

entry. Exceptions supply the interrupt vector internally. INT

instructions contain or imply the vector and allow access to

all 256 interrupts. Maskable hardware initiated interrupts

supply the 8-bit vector to the CPU during an interrupt

acknowledge bus sequence. Nonmaskable hardware inter-

rupts use a predefined internally supplied vector.

Maskable Interrupt (INTR)

The 80C286 provides a maskable hardware interrupt request

pin, INTR. Software enables this input by setting the interrupt

flag bit (IF) in the flag word. All 224 user-defined interrupt

sources can share this input, yet they can retain separate

interrupt handlers. An 8-bit vector read by the CPU during the

interrupt acknowledge sequence (discussed in System Inter-

face section) identifies the source of the interrupt.

The processor automatically disables further maskable inter-

rupts internally by resetting the IF as part of the response to

an interrupt or exception. The saved flag word will reflect the

enable status of the processor prior to the interrupt. Until the

flag word is restored to the flag register, the interrupt flag will

be zero unless specifically set. The interrupt return instruc-

tion includes restoring the flag word, thereby restoring the

original status of IF.

Non-Maskable Interrupt Request (NMI)

A non-maskable interrupt input (NMI) is also provided. NMI

has higher priority than INTR. A typical use of NMI would be

to activate a power failure routine. The activation of this input

causes an interrupt with an internally supplied vector value

of 2. No external interrupt acknowledge sequence is per-

formed.

While executing the NMI servicing procedure, the 80C286

will service neither further NMI requests, INTR requests, nor

the processor extension segment overrun interrupt until an

interrupt return (lRET) instruction is executed or the CPU is

reset. If NMI occurs while currently servicing an NMI, its

presence will be saved for servicing after executing the first

IRET instruction. IF is cleared at the beginning of an NMI

interrupt to inhibit INTR interrupts.

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