80C286_08 Datasheet, PDF (42/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
AC
Electrical
Specifications
V_CC
V_CC
=
=
+5V
+5V
±10%, T_A
±5%, T_A =
=0_o0C^oCtoto+7+07_o0C^oC(C(C808C0C28268-61-61)2,)T, _AT_A=
= -40^oC to +85^oC (I80C286-10, -12)
-40^oC to +85^oC (I80C286-16) AC Timings
are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Data Sheet Waveforms,
Unless Otherwise Specified
SYMBOL
PARAMETER
10MHz
MIN MAX
12.5MHz
MIN MAX
16MHz
MIN MAX
UNIT
TEST
CONDITION
TIMING REQUIREMENTS
1
System Clock (CLK) Period
50
-
40
-
31
-
ns
2
System Clock (CLK) LOW Time
12
-
11
-
7
-
ns At 1.0V
3
System Clock (CLK) HIGH Time
16
-
13
-
11
-
ns At 3.6V
17 System Clock (CLK) RISE Time
-
8
-
8
-
5
ns 1.0V to 3.6V
18 System Clock (CLK) FALL Time
-
8
-
8
-
5
ns 3.6V to 1.0V
4
Asynchronous Inputs SETUP Time
20
-
15
-
5
-
ns (Note 29)
5
Asynchronous Inputs HOLD Time
20
-
15
-
5
-
ns (Note 29)
6
RESET SETUP Time
19
-
10
-
10
-
ns
7
RESET HOLD Time
0
-
0
-
0
-
ns
8
Read Data SETUP Time
8
-
5
-
5
-
ns
9
Read Data HOLD Time
4
-
4
-
3
-
ns
10 READY SETUP Time
26
-
20
-
12
-
ns
11 READY HOLD Time
25
-
20
-
5
-
ns
20 Input RISE/FALL Times
-
10
-
8
-
6
ns 0.8V to 2.0V
TIMING RESPONSES
12A Status/PEACK Active Delay
1
22
1
21
1
18
ns 1, (Notes 31, 35)
12B Status/PEACK Inactive Delay
1
30
1
24
1
20
ns 1, (Notes 31, 34)
13 Address Valid Delay
1
35
1
32
1
27
ns 1, (Notes 30, 31)
14 Write Data Valid Delay
0
40
0
31
0
28
ns 1, (Notes 30, 31)
15 Address/Status/Data Float Delay
0
47
0
32
0
29
ns 2, (Note 33)
16 HLDA Valid Delay
0
47
0
25
0
25
ns 1, (Notes 31, 36)
19 Address Valid to Status SETUP Time
27
-
22
-
16
-
ns 1, (Notes 31, 32)
NOTES:
29. Asynchronous inputs are INTR, NMl, HOLD, PEREQ, ERROR, and BUSY. This specification is given only for testing purposes, to assure
recognition at a specific CLK edge.
30. Delay from 1.0V on the CLK to 0.8V or 2.0V.
31. Output load: C_L = 100pF.
32. Delay measured from address either reaching 0.8V or 2.0V (valid) to status going active reaching 0.8V or status going inactive reaching
2.0V.
33. Delay from 1.0V on the CLK to Float (no current drive) condition.
34. Delay from 1.0V on the CLK to 0.8V for min. (HOLD time) and to 2.0V for max. (inactive delay).
35. Delay from 1.0V on the CLK to 2.0V for min. (HOLD time) and to 0.8V for max. (active delay).
36. Delay from 1.0V on the CLK to 2.0V.
AC Test Conditions
TEST CONDITION
1
2
I_L (CONSTANT CURRENT SOURCE)
| 2.0mA |
-6mA (V_OH to Float)
8mA (V_OL to Float)
C_L
100pF
100pF
42