80C286_08 Datasheet, PDF (38/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
BUS CYCLE
TYPE
CLK
INTA CYCLE 1
INTA CYCLE 2
T_C
T_S
T_C
T_C
T_I
T_I
T_I
T_S
T_C
T_C
T_S
φ1 φ2 φ1 φ2 φ1 φ2 φ1 φ2 φ1 φ2 φ1 φ2 φ1 φ2 φ1 φ2 φ1 φ2 φ1 φ2 φ1 φ2
S1 • S0
M/IO,
COD/INTA
LOCK
A₂₃ - A₀
(SEE NOTE 21)
(SEE NOTE 22)
DON’T CARE
(SEE NOTE 22)
BHE
D₁₅ - D₀
READY
INTA
PREVIOUS
WRITE CYCLE
DON’T CARE
(SEE NOTE 18)
(SEE NOTE 19)
NOT READY READY
VECTOR
(SEE NOTE 20)
NOT READY READY
MCE
ALE
DT/R
DEN
NOTES:
18. Data is ignored.
19. First INTA cycle should have at least one wait state inserted to meet 82C59A minimum INTA pulse width.
20. Second INTA cycle must have at least one wait state inserted since the CPA will not drive A₂₃-A₀, BHE, and LOCK until after the first T_C
state. The CPU imposed one/clock delay prevents has contention between cascade address buffer being disabled by MCE ↓ and address
outputs.
21. Without the wait state, the 80C286 address will not be valid for a memory cycle started immediately after the second INTA cycle. The
82C59A also requires one wait state for minimum INTA pulse width.
22. LOCK is active for the first INTA cycle to prevent the 82289 from releasing the bus between INTA cycles in a multi-master system. LOCK
is also active for the second INTA cycle.
23. A₂₃-A₀ exits three-state OFF during φ2 of the second T_C in the INTA cycle.
FIGURE 29. INTERRUPT ACKNOWLEDGE SEQUENCE
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