80C286_08 Datasheet, PDF (31/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
Data Bus Control
Figures 25, 26, and 27 show how the DT/R, DEN, data bus,
and address signals operate for different combinations of
read, write, and idle bus operations. DT/R goes active
(LOW) for a read operation. DT/R remains HIGH before, dur-
ing, and between write operations.
The data bus is driven with write data during the second
phase of T_S. The delay in write data timing allows the read
data drivers, from a previous read cycle, sufficient time to
enter three-state OFF before the 80C286 CPU begins driv-
ing the local data bus for write operations. Write data will
always remain valid for one system clock past the last T_C to
provide sufficient hold time for Multibus or other similar
memory or I/O systems. During write-read or write-idle
sequences the data bus enters a high impedance state dur-
ing the second phase of the processor cycle after the last
T_C. In a write-write sequence the data bus does not enter a
high impedance state between T_C and T_S.
Bus Usage
The 80C286 local bus may be used for several functions:
instruction data transfers, data transfers by other bus mas-
ters, instruction fetching, processor extension data trans-
fers, interrupt acknowledge, and halt/shutdown. This
section describes local bus activities which have special
signals or requirements. Note that I/O transfers take place
in exactly the same manner as memory transfers (i.e. to the
80C286 the timing, etc. of an I/O transfer is identical to a
memory transfer).
HOLD and HLDA
HOLD and HLDA allow another bus master to gain control of
the local bus by placing the 80C286 bus into the T_H state. The
sequence of events required to pass control between the
80C286 and another local bus master are shown in Figure 28.
In this example, the 80C286 is initially in the T_H state as
signaled by HLDA being active. Upon leaving T_H, as sig-
naled by HLDA going inactive, a write operation is started.
During the write operation another local bus master
requests the local bus from the 80C286 as shown by the
HOLD signal. After completing the write operation, the
80C286 performs one T_I bus cycle, to guarantee write data
hold time, then enters T_H as signaled by HLDA going
active.
The CMDLY signal and ARDY ready are used to start and
stop the write bus command, respectively. Note that SRDY
must be inactive or disabled by SRDYEN to guarantee
ARDY will terminate the cycle.
HOLD must not be active during the time from the leading
edge of RESET until 34 CLKs following the trailing edge of
RESET unless the 80C286 is in the Halt condition. To
ensure that the 80C286 remains in the Halt condition until
the processor Reset operation is complete, no interrupts
should occur after the execution of HLT until 34 CLKs after
the trailing edge of the RESET pulse.
The CPU asserts an active lock signal during Interrupt-
Acknowledge cycles, the XCHG instruction, and during
some descriptor accesses. Lock is also asserted when the
LOCK prefix is used. The LOCK prefix may be used with
the following ASM-286 assembly instructions; MOVS, INS
and OUTS. For bus cycles other than Interrupt-Acknowl-
edge cycles, Lock will be active for the first and subsequent
cycles of a series of cycles to be locked. Lock will not be
shown active during the last cycle to be locked. For the
next-to-last cycle, Lock will become inactive at the end of
the first T_C regardless of the number of wait states
inserted. For Interrupt-Acknowledge cycles, Lock will be
active for each cycle, and will become inactive at the end of
the first T_C for each cycle regardless of the number of wait-
states inserted.
Instruction Fetching
The 80C286 Bus Unit (BU) will fetch instructions ahead of
the current instruction being executed. This activity is called
prefetching. It occurs when the local bus would otherwise be
idle and obeys the following rules:
A prefetch bus operation starts when at least two bytes of
the 6-byte prefetch queue are empty.
The prefetcher normally performs word prefetches indepen-
dent of the byte alignment of the code segment base in
physical memory.
The prefetcher will perform only a byte code fetch operation
for control transfers to an instruction beginning on a numeri-
cally odd physical address.
Prefetching stops whenever a control transfer or HLT
instruction is decoded by the lU and placed into the instruc-
tion queue.
In real address mode, the prefetcher may fetch up to 6 bytes
beyond the last control transfer or HLT instruction in a code
segment.
In protected mode, the prefetcher will never cause a seg-
ment overrun exception. The prefetcher stops at the last
physical memory word of the code segment. Exception 13
will occur if the program attempts to execute beyond the last
full instruction in the code segment.
If the last byte of a code segment appears on an even physi-
cal memory address, the prefetcher will read the next physi-
cal byte of memory (perform a word code fetch). The value
of this byte is ignored and any attempt to execute it causes
exception 13.
LOCK
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