80C286_08 Datasheet, PDF (47/60 Pages) Intersil Corporation – High Performance Microprocessor with Memory Management and Protection

80C286
Waveforms
BUS
CYCLE TYPE
V_OH
CLK
V_OL
S1 • S0
A₂₃ - A₀
M/IO, COD,
INTA
BHE, LOCK
D₁₅ - D₀
READY
SRDY + SRDYEN
ARDY + ARDYEN
PLCK
ALE
CMDLY
MWTC
MRDC
DT/R
DEN
READ CYCLE
ILLUSTRATED WITH ZERO
WAIT STATES
WRITE CYCLE
ILLUSTRATED WITH ONE
WAIT STATE
T_I
3 _φ2
1 ^TS
φ2
T_C
φ1
φ2
T_S
φ1
φ2
T_C
φ1
φ2
READ
(T_S OR T_S)
T_C
φ1
φ2
φ1
2
12A
12B
19
13
19
13
VALID ADDRESS
VALID ADDRESS
13
13
VALID CONTROL
VALID CONTROL
9
14
8
VALID READ DATA
11
10
VALID WRITE DATA
11
10
VALID IF T_S
15
12
11
19
19
16
17
12
13
19
20
14
13
13
13
12
12
29
30
29
30
(SEE NOTE 1)
19
20
22
24
21
23
FIGURE 34. MAJOR CYCLE TIMING
NOTE: The modified timing is due to the CMDLY signal being active.
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